Manufacturing method and structure of depletion type MOS tube

Abstract

The invention discloses a manufacturing method of a depletion type MOS tube. The method is characterized in that a channel adjusting injecting area is formed by performing a series of channel adjusting injecting and annealing and pushing; the injecting energy in the first channel adjusting injecting under the series of channel adjusting injecting is maximum, and the injecting dose is minimum, the injecting energy of every following channel adjusting injecting is gradually reduced, and the injecting dose is greatly increased, and therefore, the peak position of each channel adjusting injecting is shallower than that of each previous channel adjusting injecting; the peak value of the last channel adjusting injecting is located on the interface of a silicon and shielding oxidizing layer or located in the shielding oxidizing layer, thus the concentration of the surface of the channel adjusting injecting area is maximum and the concentration is gradually decreased in the inside direction of the silicon direction; in addition, an inversion layer cannot be formed on the surface of the channel adjusting injecting area before the depletion of the whole channel adjusting injecting area under the stop state. The invention further discloses a depletion type MOS tube. With the adoption of the method, the channel adjusting injecting area can be depleted completely under the stop state, so that the electricity leakage under the stop state can be decreased.

Description

technical field [0001] The invention relates to the field of manufacturing semiconductor integrated circuits, in particular to a method for manufacturing a depletion-type MOS tube; the invention also relates to a depletion-type MOS tube. Background technique [0002] like figure 1 Shown is a structural diagram of a depletion-type MOS transistor; taking a depletion-type NMOS transistor as an example, the basic unit structure mainly includes: a P well 5, a channel adjustment implantation region 8 formed on the surface of the P well 5, and a channel adjustment implant region 8 formed on the surface of the channel Regulate the gate oxide layer 9 and the polysilicon gate 10 on the surface of the implanted region 8, the source region 11a and the drain region 11b composed of N+ regions. [0003] Other structures are: a silicon substrate 1, an N-type epitaxial layer 2 is formed on the surface of the silicon substrate 1, an N-type buried layer (NBL) 3 and a P-type buried layer (PBL)...

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Problems solved by technology

like Figure 2C shown, is Figure 2A Schematic diagram of the depletion layer region actually depleted in the channel adjustment implantation region after implantation; it can be seen that because the concentration peak position of the channel adjustment injection region is relatively deep, the voltage applied to the polysilicon gate 10 will easily be located at the interface between the gate oxide layer and the silicon The channel adjustment injection region is depleted, and the peak region of the channel adjustment injection region is not easy to be depleted, and when the polysilicon gate 10 voltage is added to deplete the peak region of the channel adjustment injection region, the gate oxide layer and silicon The channel adjustment implant region at the interface has already begun to form an inversion layer. The formation of the inversion layer can shield the voltage applied to the polysilicon gate 10, that is, after the inversion layer is formed, it is not easy to increase the voltage of the polysilicon gate 10. The region at the bottom of the channel regulation injection region has not been depleted by depletion, such as Figure 2C As shown, the bottom of the channel adjustment injection region also includes a non-depleted region, which will form a conductive channel between the source and drain, so that the depletion MOS transistor has a large leakage, so it cannot be completely cut off

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