Bit Line Voltage Regulators in Non-Volatile Memory

Abstract

The present invention provides systems and methods that minimize write disturb conditions for unmarked memory cells in a non-volatile memory array. A bit line driver circuit is provided to control the ramp voltage applied to the bit line of the target memory cell and the adjacent bit lines of the unmarked memory cells. Various embodiments reduce a potential difference between source and drain nodes of unmarked adjacent memory cells during a write operation of a target memory cell by applying a controlled voltage signal to a previously floating bit line of an adjacent cell, The integrity of data stored in unmarked memory cells is advantageously maintained. In another embodiment, an increased source bias is applied to the "source" bit line of the target cell during the drain bias ramp-up, and then reduced to ground or near ground during the write operation.

Description

technical field [0001] The present invention relates generally to non-volatile memory, and more particularly to, by adjusting the voltage applied to a bitline of a target memory cell and adjacent bitlines of the target memory cell or adjacent memory cells during a write operation, Minimizes write disturb effects for non-volatile memory. Background technique [0002] Advances in semiconductor manufacturing processes, digital system architectures, and wireless infrastructure have primarily led to the creation of a large number of electronic products, especially consumer products, resulting in an increasing demand for the performance and density of non-volatile memory. As with many aspects of the semiconductor industry, there are continuing attempts and efforts to achieve higher device packing densities and to increase the number of memory cells on a single die, wafer or semiconductor device. At the same time, it is also desirable to increase device speed and performance. [...

AI Technical Summary

Problems solved by technology

Therefore, the increased potential difference experienced between the source and drain nodes of adjacent memory cells may cause unmarked write conditions of adjacent cells leading to severe and undesired write disturb effects

In addition, transistors with smaller physical dimensions are more sensitive, so even previously tolerant write conditions in adjacent cells can severely perturb the charging over time and thus the data in adjacent cells.

Therefore, as non-volatile memory devices are implemented with higher densities and smaller die size structures, the write disturb problem becomes more severe and more difficult to deal with

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