Accelerating simulated annealing method for integrated circuit layout

Abstract

The invention relates to an accelerating simulated annealing method for integrated circuit layout. The method includes the steps of changing the size of each dynamic exchange window of a circuit module included in an integrated circuit; according to exchange success rate at former temperature and a random number for determining whether or not certain exchange is accepted, determining the sizes of the dynamic exchange windows, and allowing the size of each dynamic exchange window engaging in exchanging to dynamically change with the random number; applying different dynamic exchange window regulating strategies according to annealing high-temperature and low-temperature phases, thus allowing a whole simulated annealing process, from high temperature to low temperature, for the layout of the circuit module.

Description

technical field [0001] The invention relates to optimizing the layout of a field programmable logic chip (FPGA), reducing the layout time, while keeping the wiring length and frequency of the circuit within a prescribed range. Background technique [0002] (1) With the continuous shrinking of integrated circuit process nodes, the number of look-up table modules (Look Up Table-LUT) included in modern field programmable logic chips (Field Programmable Gate Array-FPGA) has reached the order of millions, and embedded Many hard modules, such as digital signal processing module (Digital Signal Process-DSP), random storage module (Random Access Memory-RAM) and so on. Due to the increasing complexity of heterogeneous FPGAs, the compilation time of computer-aided design (CAD) tools is getting longer and longer, and layout is one of the most time-consuming steps in the entire compilation flow of FPGAs. The negative effect is that digital circuit design Or the prolongation of the desi...

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Problems solved by technology

[0009] In order to overcome the defective of prior art, technical scheme simulated annealing algorithm of the present invention is widely used to solve the layout problem of FPGA, but along with the increase of FPGA chip capacity, the running time of algorithm becomes unacceptable; For this reason, the purpose of the present invention It is to propose an acceleration method of simulated annealing algorithm, and use it in the layout of FPGA, reduce the layout time, and keep the wiring length and frequency of the circuit within the specified range

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