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Semiconductor device and manufacturing method thereof

A semiconductor and sidewall technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve problems such as multiple areas, and achieve the effect of reducing the area

Active Publication Date: 2018-02-06
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, compared to planar devices such as MOSFETs, the isolation between FinFETs takes up more area because each isolation requires two dummy gates.

Method used

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  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof

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Experimental program
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Embodiment Construction

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0012] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, s...

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PUM

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Abstract

Provided are a semiconductor device and a manufacturing method thereof. An example device may include: a bulk semiconductor substrate; a fin formed on the substrate; a first FinFET and a second FinFET formed on the substrate, wherein the first FinFET includes a first gate stack intersecting the fin and located at a first gate spacer on the sidewall of the first gate stack, the second semiconductor device includes a second gate stack intersecting the fin and a second gate spacer on the sidewall of the second gate stack; the first FinFET and A dummy gate spacer intersecting the fins is formed between the second FinFETs; an isolation portion self-aligned to a space defined by the dummy gate spacer, the isolation portion electrically isolates the first FinFET and the second FinFET; and is located under the isolation portion Square, the insulating layer connected to the isolation part.

Description

technical field [0001] The present disclosure generally relates to the field of integrated circuit fabrication, and more particularly, to a semiconductor device including an isolation portion that can reduce area overhead and a fabrication method thereof. Background technique [0002] With the increasing demand for multifunctional, miniaturized electronic devices, it is expected to integrate more and more devices on a wafer. However, as current devices have been miniaturized to the physical limit, it is increasingly difficult to further reduce the average area per device. Additionally, any area overhead may result in increased manufacturing costs. [0003] One of solutions to meet the miniaturization trend is a three-dimensional device, such as a FinFET (Fin Field Effect Transistor). In FinFETs, the area occupied on the wafer surface is reduced by scaling in the height direction. However, compared to planar devices such as MOSFETs, the isolation between FinFETs takes up m...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/088H01L21/762H01L21/8234
CPCH01L21/76224H01L29/6653H01L29/66545H01L29/66795H01L29/6681H01L29/7848H01L29/785H01L21/26506H01L29/0649H01L21/823431H01L21/823481H01L21/823821H01L21/823878H01L27/0886H01L27/0924H01L21/762
Inventor 朱慧珑
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI