System and method for accelerating chip interrupt controller verification

Abstract

The invention provides a system and a method for accelerating chip interrupt controller verification. The system comprises an interrupt trigger module, an interrupt release module and a simulated interrupt source module. According to the system and the method, a specific numerical value is written into a reserved register to trigger an interrupt testing event, a simulated interrupt source substitutes for a real interrupt source to forcedly trigger a real interrupt signal, an interrupt controller is started to work, and accordingly, verification of the interrupt controller is achieved rapidly; in addition, functional verification of the interrupt controller can be completed without connection of a real interrupt generation module, and hardware simulation resource cost is reduced.

Description

technical field [0001] The present invention relates to the technical field of System on a chip (SOC) chip verification, in particular to a system and method for accelerating chip interrupt controller verification. Background technique [0002] In the prior art, it is known that an interrupt controller is added to the chip in order to prevent abnormal behaviors that may occur during chip operation. In order to verify the interrupt controller, the interrupt needs to be triggered first. In the existing chip verification, the actual triggering events of some chip interrupts may take a long time to simulate, and even some interrupt triggering conditions may be very harsh and difficult to occur. For example, an ecc verification failure interrupt is designed in a Nand Flash controller. For a 40-bit ecc verification, it may be necessary to read and write 8KB data of a whole page of Flash n times before the ecc verification failure interrupt occurs. Moreover, in chip-level verific...

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Problems solved by technology

In the existing chip verification, the actual triggering events of some chip interrupts may take a long time to simulate, and even some interrupt triggering conditions may be very harsh and difficult to occur

For example, if an ecc verification failure interrupt is designed in a Nand Flash controller, for a 40-bit ecc verification, it may be necessary to read and write a whole page of 8KB of Flash data n times before the ecc verification failure interrupt occurs

Moreover, in chip-level verification, in order to trigger all interrupts, all modules associated with the interrupts need to participate in the simulation, which not only requires a long simulation time, but also consumes a lot of hardware resources

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