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Method and system for configuring PCIE bus interface in self-adaption mode

A bus interface, self-adaptive technology, applied in the field of self-adaptive configuration PCIE bus interface, can solve problems such as low efficiency, achieve high efficiency, improve flexibility and compatibility

Active Publication Date: 2015-06-17
EVOC INTELLIGENT TECH
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Problems solved by technology

[0004] Based on this, it is necessary to provide a high-efficiency self-adaption method for configuring the PCIE bus interface in order to solve the problem of low efficiency caused by repeated packaging of the Flash Image firmware and re-burning in the traditional configuration method of the PCH series platform

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  • Method and system for configuring PCIE bus interface in self-adaption mode

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Embodiment Construction

[0032] In order to make the object, technical solution and advantages of the present invention more clear, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0033] figure 1 It is a flowchart of a method for adaptively configuring a PCIE bus interface in an embodiment. The method for adaptively configuring the PCIE bus interface comprises the following steps:

[0034] Step 102, read the logic value of the speed selector composed of one or more general input and output interfaces.

[0035] Specifically, there are many types of general purpose input and output interfaces (GPIO for short). In this embodiment, GPIO68 is used to implement, but it is not limited to this, as long as it is an IO interface that can be programmed by software.

[0036] The s...

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Abstract

The invention relates to a method and system for configuring a PCIE bus interface in a self-adaption mode. The method includes the following steps of reading the logic value of a speed selector composed of one or more universal input and output interfaces, obtaining a speed value corresponding to the logic value from the pre-established configuration relation between the logic value and the speed value according to the logic value, obtaining the identification value corresponding to the speed value from the pre-established correspondence between the speed value and the identification value representing the speed value, and writing the identification value in an assigned address of the Flash area. According to the method and the system, the speed value is obtained according to the logic value, the corresponding identification value is then obtained, dynamic configuration can be achieved for different PCIE interface speeds caused when the same main board is matched with different bottom boards by packaging Flash Image firmware once without repeatedly packaging the Flash Image firmware, efficiency is high, and the flexibility and compatibility of the configuration of the main board and the bottom boards are improved.

Description

technical field [0001] The invention relates to the field of bus interface configuration, in particular to a method and system for adaptively configuring a PCIE bus interface. Background technique [0002] Products in the industrial control industry need to be equipped with various backplanes to support various PCIE (Peripheral Component Interconnect Express, the latest peripheral component interconnection) slot interfaces, such as PCIE X1, PCIE X4, PCIE X8, PCIE X16, etc., among which PCIE is The latest bus and interface standards are proposed by Intel, and the main advantage is the high data transfer rate. In order to be compatible with PCIE devices of various interfaces and to work normally in various backplanes, hardware or software is required to provide corresponding identification methods. The traditional Intel ICH (I / O controller Hub, input / output controller center) series platforms are compatible with various devices through two Strap PINs (configuration pins) in t...

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Application Information

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IPC IPC(8): G06F13/38G06F13/40
Inventor 方琼琼金立江
Owner EVOC INTELLIGENT TECH
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