Devices with multiple layers of pins in the memory mux1 layout
A technology for memory devices and memory cells, which can be used in the manufacture of electrical solid-state devices, semiconductor devices, and semiconductor/solid-state devices, and can solve problems such as oversize
Active Publication Date: 2018-01-26
TAIWAN SEMICON MFG CO LTD
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- Description
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- Application Information
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Problems solved by technology
Although 2P2E pitch at 635nm is better than 1P1E pitch at 800nm in terms of required space, for many standard cell applications 2P2E leadframes have additional electrical constraints in addition to requiring excessive pitch
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[0028] The making and using of various embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are examples of specific ways of making and using, and do not limit the scope of the invention.
[0029] Additionally, the present invention may repeat reference numerals and / or characters in multiple instances or utilize the same last two digits but different preceding digits (or digits) to designate corresponding components. This repetition is used for simplicity and clarity to indicate corresponding objects and by itself does not indicate a relationship between the various embodiments and / or configurations. Furthermore, in the context of the present invention, a component formed on, connected to, and / or coupled to another component may include embodiments in which the components are formed in d...
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The present invention discloses a device with multiple layers of pins in the memory MUX1 layout. An integrated circuit (IC) memory device comprising: a first conductive layer; a second conductive layer electrically connected to the first conductive layer, the second conductive layer being formed over the first conductive layer; spaced apart from the second conductive layer A third conductive layer, the third conductive layer is formed above the second conductive layer; a fourth conductive layer electrically connected to the third conductive layer, the fourth conductive layer is formed above the third conductive layer; formed on the first conductive layer or 2P2E lead frame in the second conductive layer and electrically connected to the first conductive layer or the second conductive layer; and formed in the third conductive layer or the fourth conductive layer and electrically connected to the third conductive layer or the fourth conductive layer 1P1E lead frame.
Description
technical field [0001] The present invention generally relates to the field of semiconductor technology, and more particularly, to integrated circuit memory devices. Background technique [0002] Integrated circuit (IC) process and packaging constraints associated with decreasing component sizes make it increasingly difficult to maintain the previous pin-pad (leadframe) spacing (pitch). For example, single exposure and single etch (1P1E) lithography limits the leadframe pitch to 800nm for 5 specific pins, but electrically connects to static random access memory (SRAM) in some newer standard cell libraries. ) The 5 input / output (I / O) pins of the multiplexer 1 (MUX1) memory cell only allow a total lead frame spacing of 450nm to 720nm, thus not satisfying 5 I / O pins. [0003] 1P1E lithography limits the 5-pin leadframe pitch to 800nm, while double exposure and double etch (2P2E) lithography limits the 5-pin leadframe pitch to 635nm. Although 2P2E pitch at 635nm is better th...
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IPC IPC(8): H01L27/11
CPCH01L2924/0002H01L27/0203H10B10/00H01L2924/00H01L21/0274H01L21/47573H01L2924/1437H01L23/53204H01L23/528H01L23/49811H01L23/49827H01L23/50H01L23/5226
Inventor 廖宏仁陈蓉萱田倩绮吴经纬蔡睿哲郑宏正王中兴
Owner TAIWAN SEMICON MFG CO LTD