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LDO (low dropout regulator) circuit with external capacitance detecting function

A technology of external capacitance and level detection, applied in the direction of adjusting electrical variables, control/regulation systems, instruments, etc., can solve the problems of increasing the production complexity and cost of end products, abnormal LDO operation, and insufficient capacitance value, etc., to achieve The effect of high reliability, low cost and convenient operation

Active Publication Date: 2015-07-01
上海菱沃铂智能技术有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, on the end product, there will be such a situation: if the capacitance Cext of the Vlow node of the board-level circuit is weakly welded, or the capacitance of the welded capacitance is insufficient or damaged, the LDO will not work normally, the AC response will be poor, and the output voltage will oscillate.
Therefore, in order to ensure product quality, it is necessary to add a capacitance test circuit to the board-level circuit, which increases the production complexity and cost of the terminal product.

Method used

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  • LDO (low dropout regulator) circuit with external capacitance detecting function
  • LDO (low dropout regulator) circuit with external capacitance detecting function

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Embodiment

[0021] Such as figure 2 , an LDO circuit with an external capacitance detection function, including a built-in voltage reference source, an amplifier, a linear switch M1 (PMOS), a voltage divider feedback loop R1 and R2, a core circuit and a parasitic capacitance C1, a preset external capacitance Cext, and a capacitor Detection switch S1, level detection circuit, clock and timing circuit. The built-in voltage reference source is connected to the negative terminal of the amplifier, the positive terminal of the amplifier is connected to the R1R2 feedback node, the output terminal of the amplifier is connected to the gate of M1, the source and drain of M1 are respectively connected to the input and output nodes Vhigh and Vlow of the LDO, and the core The circuit and parasitic capacitor C1 and the preset external capacitor Cext are connected to Vlow; the capacitance detection switch is connected in parallel to both ends of R1, the output of the amplifier is connected to the level...

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PUM

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Abstract

The invention relates to an LDO (low dropout regulator) circuit with an external capacitance detecting function. The LDO circuit comprises a built-in voltage reference source, an amplifier, a linear switch M1, partial pressure feedback loops R1 and R2, a core circuit and a stray capacitance C1, and a preset plug-in capacitor Cext; the LDO circuit further comprises a capacitance detecting switch S1, a level detection circuit, a clock and time sequence circuit; capacitance detecting switches are linked to both ends of R1 in parallel and connected with the clock and time sequence circuit, one end of the level detection circuit is connected to the output end of the amplifier, and the other end is connected with the clock and time sequence circuit. Compared with the prior art, the LDO circuit is convenient to operate, high in reliability, low in cost, and the like.

Description

technical field [0001] The invention relates to an LDO circuit, in particular to an LDO circuit with an external capacitance detection function. Background technique [0002] LDO is used to generate a relatively stable output voltage, usually including a voltage reference source, an amplifier, a linear switch (transistor or MOS tube) and a voltage divider feedback loop. Through the feedback loop, the output voltage is stabilized to a preset voltage value. Usually, a capacitor is attached to the output voltage node as the main pole of the entire feedback loop. [0003] With the increasing integration of CMOS, there are more and more ways to build LDO in the chip to obtain a stable core voltage, such as figure 1 , Vhigh is the LDO input voltage, Vlow is the LDO output voltage, and is also the power supply voltage of the core circuit. C1 is the parasitic load capacitance inside the chip, and its capacitance is generally in the order of 10pF to 10nF; Cext is the external capa...

Claims

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Application Information

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IPC IPC(8): G05F1/56
Inventor 梁青武
Owner 上海菱沃铂智能技术有限公司
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