A delay locked loop

Abstract

The invention provides a delay locked loop, comprising: a digitally controlled delay chain, which adjusts the delay of the digitally controlled delay chain, and outputs a clock signal in a corresponding output mode; a phase detection logic circuit, according to the reference clock and Whether the delay difference of the feedback clock falls within the locking accuracy range Generate and output the lead or lag signal, lock logic signal; digitally control the delay chain control code generation circuit, and initially generate the rough delay chain control code according to the cycle size of the reference clock , then generate said other fine-tuning delay chain control codes according to the delay difference between the reference clock and the feedback clock, and finally adjust the fine-tuning delay chain control codes according to the lead or lag signal; the multi-mode selection control circuit, according to the working mode The selection signal control circuit is in a corresponding working mode, and at the same time combined with the locking logic signal to control the multi-mode selection control circuit to generate and output the first-bit fine-tuning delay chain control code in the corresponding working mode.

Description

technical field

[0001] The invention relates to the technical field of integrated circuits in the electronics industry, in particular to a delay-locked loop. Background technique

[0002] The clock signal of a system or circuit is often used as a reference quantity for synchronously performing timing and ensuring error-free high-speed operation. When the internal circuit uses the clock signal source of the external circuit, the internal circuit often produces clock signal skew due to the timing gap between the external clock signal and the internal clock signal. The delay locked loop can compensate the skew of the clock signal so that the phase of the internal clock signal is equal to the phase of the external clock signal.

[0003] The basic idea of ​​a delay-locked loop is to delay the output clock so that it can be perfectly aligned with a reference clock or produce a definite phase-shifted output. At the same time, because DLL has the advantage of being less susceptibl...

Images