Layout method and device capable of achieving clean supply for chip interior analog modules

Abstract

The invention provides a layout method and device capable of achieving clean supply for chip interior analog modules. The device comprises N chips and a power source ring with N layers of metal rings. The first layer of the metal rings and the N layer of the metal rings are single metal rings, and each of the other layers of the metal rings (from the second layer to the (N-1) layer) comprise first sub metal rings, second sub metal rings and third sub metal rings. The Nth layer of the power source ring is grounded, the first layer, the N layer and the first sub metal rings and the third sub metal rings in the second layer to the (N-1) layer are connected by means of through holes and then grounded. The second sub metal rings in the second layer to the (N-1) layer are separated from the metal rings of the grounded layers and used as signal lines or power lines. The third sub metal rings of a part of the layers are disconnected at proper positions, and the signal lines or the power lines are connected with the chip interior analog modules at the disconnection positions. By means of the method and device, the length and width of the chips can be reduced by more than 30 micrometers, cost is effectively reduced, and the precision of the analog modules is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor layout design, in particular to a layout method and a device for realizing interference-free power supply of an analog module inside a chip. Background technique [0002] There are multiple analog modules inside the system-level chip. The general power planning scheme adopts a point-to-point method. The chip power supply will be distributed to various positions inside the chip, which wastes chip resources, increases costs, and increases the number of metal layers of the chip. The general analog power wiring method in the chip generally starts from the power pad, uses an independent power line to start from the edge of the chip as far as possible away from the noisy module, walks to the position of the analog module, and connects to the power supply of the analog module. The power line runs from the inside of the chip and passes through various digital modules, which will be coupled with the ...

AI Technical Summary

Problems solved by technology

[0002] There are multiple analog modules inside the system-level chip. The general power supply planning scheme adopts a point-to-point method. The chip power supply will be distributed to various positions inside the chip, which wastes chip resources, increases costs, and increases the number of metal layers of the chip.

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