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Redundancy evaluation circuit for semiconductor devices

A technology for evaluating circuits and oxide semiconductors, applied in information storage, static memory, instruments, etc., can solve the problem of large layout area of ​​redundant evaluation circuit 1, and achieve the effect of reducing the layout area

Active Publication Date: 2018-05-29
ELITE SEMICON MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

exist figure 1 The redundant evaluation circuit 1 in requires a plurality of multiplexers 12, a plurality of PMOS transistors P11 to P1k, P21 to P2k, P31 to P3k, and a plurality of NMOS transistors N11 to N1k, so Larger layout area for redundant evaluation circuit 1

Method used

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  • Redundancy evaluation circuit for semiconductor devices
  • Redundancy evaluation circuit for semiconductor devices
  • Redundancy evaluation circuit for semiconductor devices

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Embodiment Construction

[0050] Reference examples will be presented and described in detail herein to explain embodiments of the present invention, and the following examples will be explained with reference to the accompanying drawings. The same or similar components, signals or terminals, etc. will be marked with the same or similar component symbols as much as possible.

[0051] An embodiment of the present invention provides a redundancy evaluation circuit for a semiconductor device, which has a smaller layout area than a conventional redundancy evaluation circuit. In addition, another embodiment of the present invention also provides a semiconductor device having the redundancy evaluation circuit. In various embodiments, multiple fuses in the fuse box share one reverse latch and one pre-charge transistor, thus saving several transistors. In addition, each fuse is coupled to an optional transistor, thus saving several multiplexers. Therefore, the redundant evaluation circuit of the embodiment o...

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Abstract

A redundancy evaluation circuit for a semiconductor device. The redundancy evaluation circuit has (m+1) fuse boxes and comparators, wherein m fuse boxes output fuse state address signals, and the other fuse box outputs comparator enabling signals. Each fuse box has a common-level circuit and k redundant units, and the k redundant units share the pre-charge transistor and the reverse latch of the common-level circuit, and the fuse in the selected redundant unit affects the corresponding fuse The output of the silk box. The comparator enabled by the comparator enable signal compares the fuse state address number and the defective device address signal to generate a redundant enable signal. The redundant evaluation circuit has a smaller layout area.

Description

technical field [0001] The present invention relates to a semiconductor device, in particular to a redundancy evaluation circuit of the semiconductor device. Background technique [0002] The development of science and technology enables semiconductor integrated circuits to cover more circuit elements in a given silicon area. However, as the number of circuit components increases, it becomes more difficult to reduce and eliminate defects of the circuit components. [0003] To achieve efficient space allocation, circuit designers strive to reduce the size of individual circuit elements to increase the actual but unused space, and the reduction in size makes these circuit elements more susceptible to defects, wherein the defects are in the Caused by impurities in the material during the manufacturing process. However, testing procedures at the semiconductor component level or after semiconductor packaging can make multiple defects identifiable throughout the integrated circu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C17/16
Inventor 赖亚群
Owner ELITE SEMICON MEMORY TECH INC