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Fin field effect transistor with multi-layer fin for multi-value logic applications and method of forming the same

A fin and underlying technology, applied in the field of fin field effect transistor technology nodes, can solve the problems of complex and expensive transistors

Active Publication Date: 2018-09-28
GLOBALFOUNDRIES U S INC MALTA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Additionally, forming a multiple V t The individual transistors are complex and expensive

Method used

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  • Fin field effect transistor with multi-layer fin for multi-value logic applications and method of forming the same
  • Fin field effect transistor with multi-layer fin for multi-value logic applications and method of forming the same
  • Fin field effect transistor with multi-layer fin for multi-value logic applications and method of forming the same

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Embodiment Construction

[0040] The following description is for purposes of explanation and numerous specific details are set forth in order to provide an understanding of the example embodiments. It should be apparent, however, that example embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the embodiments. Furthermore, all numbers expressed in the specification and claims, such as amounts, ratios and numerical characteristics of ingredients, reaction conditions, etc., are in any case modified by the term "about" unless otherwise stated.

[0041] The present invention addresses and solves the current problem of large footprint required to form a multi-valued logic transistor. According to embodiments of the present invention, multiple threshold voltages (Vt) can be achieved by forming multilayered fins with increasing germanium o...

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Abstract

The present invention relates to a fin field effect transistor with multi-layer fins for multi-valued logic applications and a method of forming the same, wherein a method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming a plurality of fins on a silicon substrate, each fin being covered with a hard mask; filling the space between the fins and the hard mask with oxide; removing the hard mask and leaving each The fins are recessed, forming pockets in the oxide above each fin; in each of the pockets, a multi-layer silicon base layer is formed, the silicon base layers having a gradually increasing ratio of germanium or carbon content from the bottom to the top layer or Gradually decreasing doping concentration; chemical mechanical polishing of the top of the fin to achieve planarization; recessing the oxide to a depth slightly lower than the top of the fin and making the fin thickness equal to the thickness of each silicon base layer thickness; and forming a high-k dielectric gate and a metal gate electrode above the multi-layer silicon base layer.

Description

technical field [0001] The present invention is concerned with multi-valued logic (MVL) transistors. The present invention relates to FinFET technology nodes applicable to 14 nanometer (nm) - extreme mobility (14XM) and 10 nm and beyond. Background technique [0002] Transistor structures that are traditionally capable of handling multi-valued logic states are often formed as Figure 1A and Figure 1B shown, passing multiple threshold voltages of the transistor (e.g., V t0 , V t1 and V t2 ) and a shared gate electrode 101. Therefore, an NFET actually has N transistors sharing a common gate (ie, has the footprint of N transistors). Such as Figure 1C as shown, Figure 1A and Figure 1B Process four levels of logic signals (or 2 bits), 00, 01, 10, and 11, at the input voltage V g The 2-bit information in is determined by the output current I d Indicated by 2 bits of information. Although multi-valued logic is far more efficient and faster than current binary logic, e...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L21/336
CPCH01L21/02532H01L21/0262H01L21/02639H01L21/823431H01L21/823481H01L27/0886H01L21/02529H01L21/02576H01L21/02579H01L21/3086H01L29/66795H01L29/785H01L29/1054H01L29/7848H01L29/161H01L21/30625H01L21/3065H01L21/308H01L27/0924H01L29/0653H01L29/0847H01L29/1608H01L29/165
Inventor M-h·齐A·雅各布A·保罗
Owner GLOBALFOUNDRIES U S INC MALTA