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A low-voltage, high-performance, low-power C-unit

A high-performance, low-power technology, applied in the field of C units, can solve the problems of no consideration of power consumption suppression technology, large dynamic power consumption and leakage power consumption, and incompatibility, so as to reduce static power consumption and reduce dynamic power consumption. , the circuit structure is simple and clear

Active Publication Date: 2017-10-31
NINGBO UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The traditional weak feedback C unit includes a pull-up unit composed of two PMOS transistors, a pull-down unit composed of two NMOS transistors, and two inverters. The traditional weak feedback C unit has a simple structure and fast speed, but it does not have Considering the power consumption suppression technology, if it is applied in a low-voltage (0.5V) environment, the dynamic power consumption and leakage power consumption are large, and it is not suitable for a low-voltage and low-power consumption environment

Method used

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  • A low-voltage, high-performance, low-power C-unit
  • A low-voltage, high-performance, low-power C-unit
  • A low-voltage, high-performance, low-power C-unit

Examples

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Embodiment

[0014] Example: such as image 3 As shown, a low-voltage, high-performance, low-power C unit includes a PMOS pull-up unit and an NMOS pull-down unit, the PMOS pull-up unit includes a first PMOS transistor P1 and a second PMOS transistor P2, and the NMOS pull-down unit includes a first NMOS transistor N1 and the second NMOS transistor N2, the source of the first PMOS transistor P1, the substrate of the first PMOS transistor P1 and the substrate of the second PMOS transistor P2 are connected to the power supply, the drain of the first PMOS transistor P1 and the second The source of the PMOS transistor P2 is connected, the drain of the second PMOS transistor P2 is connected to the drain of the first NMOS transistor N1, the source of the first NMOS transistor N1 is connected to the drain of the second NMOS transistor N2, and the first NMOS transistor The substrate of N1, the source of the second NMOS transistor N2, and the substrate of the second NMOS transistor N2 are all grounde...

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Abstract

The invention discloses a C unit with low voltage, high performance and low power consumption, which comprises a PMOS pull-up unit, an NMOS pull-down unit, a signal drive gate, a weak feedback gate and a ground feedback gate; The phase device is used to save data, the ground feedback gate is used to control the working state of the signal drive gate and the weak feedback gate, when the first signal input terminal and the signal input terminal of the low-voltage high-performance low-power consumption C unit are connected to the input signal, the signal The driving gate and the weak feedback gate either work in a weak working state to reduce the current, or the power consumption is drastically reduced by the ground feedback gate; the advantage is that the dynamic power consumption and leakage power consumption are small, and can be applied in a low-voltage environment. NCSU PTM 45nm CMOS process, power supply voltage 0.5V, when the frequency of the first input signal connected to the first signal input terminal is 100MHz, and the frequency of the second input signal B connected to the second signal input terminal is 50MHz, and weak feedback Compared with the C unit, the dynamic power consumption is reduced by 49.6%, the static power consumption is reduced by 11.1%, and the performance is improved by 34.3%.

Description

technical field [0001] The invention relates to a C unit, in particular to a C unit with low voltage, high performance and low power consumption. Background technique [0002] As the integrated circuit process enters the nanometer scale, the chip integration level increases and the clock frequency increases, resulting in a rapid increase in chip dynamic power consumption. The increase of dynamic power consumption has brought many problems, such as: the temperature rise caused by the increase of power consumption will reduce the reliability and stability of the device, and also bring about packaging and heat dissipation problems. Another problem with increased chip power consumption is excessive energy consumption and environmental protection. With the widespread use of electronic equipment, the cost of electricity for electronic equipment will exceed the cost of hardware in the next few years. In addition, with the widespread use of battery-powered devices such as laptops,...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/0948
Inventor 邬杨波董恒锋杨金龙赵旭
Owner NINGBO UNIV
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