A method of manufacturing an embedded silicon germanium structure

Abstract

The invention discloses a fabrication method of an embedded germanium-silicon structure. The fabrication method includes the following steps that: a hard mask layer is formed on a substrate, and the hard mask layer on source and drain regions of the substrate is removed selectively; with the hard mask layer adopted as a mask, the source and drain regions of the substrate are etched, so that a U-shape groove can be formed; a germanium and silicon layer is formed in the U-shaped groove through epitaxial growth, and the germanium and silicon layer can cover the semiconductor substrate at the bottom of the U-shaped groove and exposes the semiconductor substrate at the side wall of the U-shaped groove; a silicon layer is formed at the side wall and bottom of the U-shaped groove through epitaxial growth; and the semiconductor substrate exposed at the side wall of the U-shaped groove is partially etched through adopting a crystal orientation selective etching process, so that a second sigma-shaped groove can be formed. According to the fabrication method of the invention, after the silicon-germanium protective layer is formed at the bottom of the U-shaped groove, the thin silicon layer is formed through epitaxial growth, and therefore, the defect of defective pixel generation at the SiGe / Si junctions in a subsequent etching process can be avoided, and the embedded germanium-silicon structure can be optimized, and the stability of the techniques can be guaranteed.

Description

technical field [0001] The invention belongs to the field of semiconductor integrated circuit manufacturing equipment, and relates to a method for manufacturing an embedded silicon germanium structure. Background technique [0002] With the continuous development of integrated circuit technology, more devices will be integrated on the chip, and the chip will adopt faster speed. Driven by these requirements, the geometric size of devices will continue to shrink, and new materials, new technologies and new manufacturing processes will be continuously used in the chip manufacturing process. At present, the preparation of semiconductor devices has been developed to the nanometer level, and the preparation process of conventional devices has gradually matured. [0003] Applying stress to the CMOS channel region of a semiconductor device can improve the mobility of CMOS carriers. In the process of preparing CMOS, epitaxial silicon germanium (e-SiGe) is carried out in the source ...

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Problems solved by technology

[0004] However, during epitaxial growth and other integration processes, dead point defects will be generated at the SiGe / Si junction, which will weaken the stress in the channel, thereby affecting the performance of PMOS transistors

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