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Phase-locked loop with low phase noise

A low-phase noise, phase-locked loop technology, applied in the direction of automatic power control, electrical components, etc., can solve the problem of large phase noise of the phase-locked loop, achieve small high-frequency phase detection dead zone, get rid of the limitation of phase detection speed , the effect of reducing phase noise

Active Publication Date: 2015-09-09
SUN YAT SEN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to provide a phase-locked loop with low phase noise, which aims to solve the technical defect of excessive phase noise of the existing phase-locked loop

Method used

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  • Phase-locked loop with low phase noise
  • Phase-locked loop with low phase noise
  • Phase-locked loop with low phase noise

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Embodiment Construction

[0025] The embodiments of the present invention will be further described below in conjunction with the accompanying drawings.

[0026] see figure 2 , figure 2 It is a phase-locked loop with low noise phase provided by the embodiment of the present invention. exist figure 2 In the illustrated embodiment, the low phase noise PLL of this structure includes a frequency digital converter 110, an oscillator frequency calibrator 120, a loop bandwidth calibrator 130, a digital oscillator 190, a phase detector 140, a time digital converter 150 , filter 160 and clock distribution module 180 .

[0027] exist figure 1 In the illustrated embodiment, the input terminal of the frequency digitizer 110 receives an input signal, and the output terminal is respectively connected to the input terminals of the oscillator frequency calibrator 120 and the loop bandwidth calibrator 130 . The output terminal of the oscillator frequency calibrator 120 is connected to the input terminal of the ...

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Abstract

The invention discloses a phase-locked loop with low phase noise. The phase-locked loop comprises a frequency digital converter, an oscillator frequency calibrator, a loop bandwidth calibrator, a digital oscillator, a phase discriminator, a time to digital converter, a filter and a clock distributing module, wherein an input end of the frequency digital converter receives an input signal, and an output end of the frequency digital converter is connected with input ends of the oscillator frequency calibrator and the loop bandwidth calibrator; an output end of the oscillator frequency calibrator is connected with an input end of the digital oscillator, and an output end of the loop bandwidth calibrator is connected with a control end of the filter. The phase-locked loop with low phase noise of the embodiment of the invention uses the time to digital converter with high resolution to realize conversion of phase difference, replaces a traditional digital phase discriminator, and is free from the limitation of system clock frequency to phase discriminating speed to further reduce size of a high-frequency phase discrimination dead zone, thereby greatly reducing the phase noise of the phase-locked loop.

Description

technical field [0001] The invention relates to a phase-locked loop structure in the field of electronic technology, in particular to a phase-locked loop with low phase noise. Background technique [0002] A phase-locked loop is a feedback system in which a voltage-controlled oscillator (VCO) and a phase comparator are interconnected such that the oscillator output maintains a constant phase angle with respect to a reference signal. PLLs are used in many fields, such as wireless communication, digital TV, broadcasting and other fields. as attached figure 1 As shown, a phase-locked loop circuit usually consists of the following modules: phase detector (PD), low-pass filter (LPF), voltage-controlled oscillator (VCO) and feedback loop (usually divided by a frequency divider (DIV) accomplish). The phase detector compares the frequency and phase of the input reference signal and the signal of the feedback loop, and outputs a signal representing the difference between the two t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/08H03L7/099
Inventor 王自鑫陈弟虎何振辉何裕宁王敏刘伍兵
Owner SUN YAT SEN UNIV
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