Fine pitch copper cylinder dimpling point preparation technology

Abstract

The invention relates to one kind of fine pitch copper cylinder dimpling point preparation technology characterized in that the following steps are comprised: (1), a Ti / Cu seed layer is electroplated on the surface of a wafer; (2) a copper layer is deposited on the surface of the Ti / Cu seed layer; (3), a brazing filler metal layer is prepared on the surface of the copper layer; (4), a photoresist layer is coated on the surface of the brazing filler metal layer; (5), opening technology is applied on the photoresist layer to form openings which extend from the upper surface of the photoresist layer to the lower surface of the photoresist layer; the size, the quantity and the distribution of the photoresist layer saved after opening making are consistent with the size, the quantity and the distribution of copper columns which need to be made; (6), etching is carried out on the opening portions, and the brazing filler metal layer, the copper layer and the Ti / Cu seed layer below the opening is etched to expose the upper surface of the wafer; (7), the residual photoresist layer is peeled off; and (8) backflows enable copper column dimpling points to form. According to the invention, preparation of the copper column dimpling points can be completed in batch; the production efficiency is raised; dimpling point manufacturing of ternary or multicomponent alloy materials so as to satisfy application of different products.

Description

technical field [0001] The invention relates to a fine-pitch copper pillar micro-bump preparation process, which belongs to the technical field of high-density electronic packaging. Background technique [0002] With the continuous increase of IC chip bandwidth, more and more I / O ports need to be drawn out. Traditional micro-bump technology and wire bonding technology have been difficult to meet the needs of high-bandwidth IC chips. Therefore, fine-pitch, high-density micro-bump technology has begun to be widely used. In the micro-bump structure, copper pillar bump technology is the most widely used. Since Intel first used it in processors in 2006, copper pillar bumps have gradually been widely used in wafer-level bump manufacturing and micro-assembly processes of Flip-chip (flip-chip) technology. Copper pillar bump is composed of copper pillar and top solder cap, which has a height-to-diameter ratio greater than 1:1, while the proportion of solder cap is small, and the c...

AI Technical Summary

Problems solved by technology

The biggest advantage of this process is that the cost is very low. However, the process is not yet mature, and it is also performed on a single chip, so the efficiency is low.

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