Radio frequency ldmos device and manufacturing method thereof

Abstract

The invention discloses a radio frequency LDMOS device. The shielding dielectric layer is formed by the following process: sequentially forming the first oxide layer, the second nitride layer and the third oxide layer which form the shielding dielectric layer; A mask; using the first mask as a mask to wet etch the third oxide layer; using the first mask as a mask to etch the second nitride layer by a dry etching process; removing the first The mask is formed by stacking the first oxide layer, the second nitride layer and the third oxide layer outside the second side of the polysilicon gate after removing the first mask to form a shielding dielectric layer. The middle thickness of the shielding dielectric layer is thick and the thickness on both sides is thin. . The invention also discloses a manufacturing method of the radio frequency LDMOS device. The invention can reduce on-resistance, increase saturation current and breakdown voltage, effectively increase output power, reduce output capacitance, improve device efficiency and gain, reduce electric field intensity at polysilicon gate boundary, and prevent HCI failure.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a radio frequency LDMOS device; the invention also relates to a method for manufacturing the radio frequency LDMOS device. Background technique [0002] Radio frequency lateral field effect transistor (RF LDMOS) is widely used in radio frequency high power fields such as base stations and radio and television transmissions. Using power array and multi-chip synthesis, the output power of the product can reach more than 500 watts. The RF performance and reliability of RF LDMOS are between The contradiction is the focus of the study. On-resistance and output capacitance are the main factors affecting the efficiency of RF LDMOS transistors. Reducing the on-resistance and output capacitance reduces the power loss from both, increasing the efficiency and gain of the device. Reducing the gate-source capacitance and feedback capacitance can effectively impr...

AI Technical Summary

Problems solved by technology

where the dashed circle 214 corresponds to figure 1 At the side of the drain end of the polysilicon gate 106, the dotted circle 213 is located on the side of the drain end of the polysilicon gate 106, which is closer to the outside of the drain region 106b; after increasing the thickness of the shielding dielectric layer in the dotted circle 214, the electric field intensity on the surface of the silicon chip gradually increases , which causes a strong electric field at the boundary of the polysilicon gate 106, leading to hot carrier breakdown (HCI) failure

[0008] It can be seen from the above that increasing the thickness of the shielding dielectric layer under the G-shield can reduce the on-resistance, increase the saturation current and breakdown voltage, and can effectively increase the output power; at the same time, the output capacitance can be reduced, which can improve the efficiency and gain of the device, but At the same time, a strong electric field will be caused at the poly boundary, which will cause the HCI to fail

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