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SRAM (static random access memory) storage unit, SRAM memory and control method therefor

A memory unit and memory technology, applied in static memory, digital memory information, information storage, etc., can solve the problems of increasing the size of the memory cell array, increasing the number of transistors, unfavorable integrated circuit integration and chip size miniaturization, etc., and achieve bit line Effect of small cell size and improved stability

Inactive Publication Date: 2015-11-25
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Compared with the 8T structure, the 7T structure lacks a pass transistor (PG) 260, and other settings are identical. Although the SRAM memory cells of the 7T structure and the 8T structure have improved stability, the number of transistors increases, and the memory cell array The size also increases accordingly, which is not conducive to the improvement of integrated circuit integration and the miniaturization of chip size

Method used

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  • SRAM (static random access memory) storage unit, SRAM memory and control method therefor
  • SRAM (static random access memory) storage unit, SRAM memory and control method therefor
  • SRAM (static random access memory) storage unit, SRAM memory and control method therefor

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Embodiment 1

[0036] According to one aspect of the present invention, the present invention provides a kind of SRAM memory cell comprising: word line pair, and described word line pair comprises write word line 380 and read word line 370; Bit line pair, described bit line pair comprises write position line 330 and read bit line 340;

[0037] a memory cell located between the pair of word lines and the pair of bit lines, the memory cell includes a read end and a write end;

[0038] The read transfer transistor 360 at the read end is controlled by the read word line 370 to realize information reading, and the write transfer transistor 350 at the write end is controlled by the write word line 380 to realize information input.

[0039] Specifically, the size of the storage unit largely determines the size of the SRAM chip, therefore, it is necessary to make the size of the storage unit as small as possible. The memory cell may be constituted by an inversion cell for inverting the potential of...

Embodiment 2

[0051] The present invention also provides an SRAM memory, the SRAM memory includes the SRAM storage unit described in Embodiment 1, wherein the memory may include several SRAM storage units, wherein the SRAM storage unit may be arranged along a row oriented or otherwise arranged.

[0052] The present invention also provides a control method of the SRAM memory, the control method comprising:

[0053] When performing a write operation on the selected one of the memory cells, the write word line corresponding to the selected one is set to a high potential, and the information transmitted by the peripheral circuit to the pair of bit lines is used as input; and

[0054] When performing a read operation on a selected one of the plurality of memory cells, the read word line corresponding to the selected one is set to a low potential, the read bit line is set to a high potential, and the unselected one is set to a high potential. The read word line corresponding to one of them is se...

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Abstract

The present invention provides an SRAM storage unit, an SRAM memory and a control method therefor. The SRAM storage unit comprises: a word line pair, wherein the word line pair comprises a write word line and a read word line; a bit line pair, wherein the bit line pair comprises a write bit line and a read bit line; and a storage unit positioned between the word line pair and the bit line pair, wherein the storage unit comprises a read-out end and a write-in end, a read transmission transistor of the read-out end is controlled by means of the read word line so as to implement reading of information, and a write transmission transistor of the write-in end is controlled by means of the write word line so as to implement input of the information. The advantages of the SRAM storage unit are that compared to a 6T structural unit in the prior art, read static noise margin (RSNM) of the SRAM storage unit is improved and the stability of the storage unit is improved; and compared to 7T and 8T structural units in the prior art, a bit line unit is smaller in size, which is beneficial for improvement on the integration level of an integrated circuit and miniaturization of a chip size.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an SRAM storage unit, an SRAM memory with the SRAM storage unit and a control method for the SRAM memory. Background technique [0002] With the continuous development of digital integrated circuits, on-chip integrated memory has become an important part of digital systems. SRAM (StaticRandomAccessMemory, static random access memory) has become an indispensable and important part of the on-chip memory with its advantages of low power consumption and high speed. SRAM can hold data as long as it is powered, there is no need to constantly refresh it. [0003] The overall structure of SRAM can be divided into two parts: memory cell array and peripheral circuit. In SRAM, the storage unit is the most basic and important component. The number of memory cells included in the array and the stability of the memory cells are two important factors affecting the performance of ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/416
Inventor 陈金明
Owner SEMICON MFG INT (SHANGHAI) CORP