Device structure and fabrication method of three-dimensional integrated circuit
A device structure and integrated circuit technology, applied in the direction of electric solid-state devices, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as limited capacitor area, capacitor storage capacity, internal resistance and other indicators that cannot meet device production requirements, etc.
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[0046] The core idea of the present invention is that circuit elements are arranged on the surface of the wafer backside in the non-device area.
[0047] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.
[0048] Specifically, such as figure 1 The schematic diagram of the wafer bonding structure shown: the bonded wafer specifically includes a first wafer 1 and a second wafer 2, the first wafer 1 is located above the second wafer 2, and the front sides of the two wafers mutual bonding.
[0049] In an actual production process, a wafer surface provided with device structures is used as the front surface of the wafer and a back surface is set relative to the front surface. For details, reference may be made to the prior art.
[0050] In an embodiment of the present invention, the back side of the first wafer 1 or the back side of the second wafer 2 or ...
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