High-voltage start-up circuit with adjustable start-up time

Abstract

A high voltage start-up circuit with adjustable start-up time, wherein, the drain electrode of the first NMOS transistor is connected with a first terminal of the first resistor, a gate electrode of the second NMOS transistor and a negative terminal of the diode; a source electrode of the first NMOS transistor, together with a positive terminal of the diode, is connected to the power ground; a drain electrode of the second NMOS transistor, together with a second terminal of the first resistor, is connected with a port SW of a chip; a source electrode of the second NMOS transistor, together with a first terminal of the second resistor, is connected with a power port VDD of the chip. The circuit can adjust the start-up time and the restart time of the chip flexibly.

Description

Technical field [0001] The invention relates to a high-voltage startup circuit with adjustable startup time, which is suitable for power management integrated circuits and belongs to the technical field of power semiconductors. Background technique [0002] The working waveform corresponding to the traditional starting circuit starting method, such as figure 1 At the beginning of the T1 time period, the system is powered on and the start-up begins, and the VDD voltage continues to rise. At the end of the T1 time period, the VDD voltage reaches the threshold VTH1, and the chip works normally. The T2 time period is the normal working stage. An abnormal situation occurs at a certain moment in T2, and the VDD voltage drops. When the VDD voltage drops to the threshold VTH2, the undervoltage latch signal UVLO is valid and the chip enters the abnormal restart phase T3. At the end of T3, the VDD voltage rises to VTH1 again, and the chip works normally again and detects abnormal condition...

AI Technical Summary

Problems solved by technology

[0003] Although the traditional startup method can ensure the chip starts normally and restarts under abnormal conditions, the time for this startup method to start the chip when it is powered on and restart under abnormal conditions is fixed and cannot be adjusted, and the chip is powered on and restarted under abnormal conditions. same speed

For example, if the power-on starts quickly, the restart time under abnormal conditions will also be very short, which will lead to large input power and large power loss during restart under abnormal conditions; if in order to reduce power consumption under abnormal conditions, slow down If the restart speed is lower, the power-on startup speed will also slow down, which may not meet the application requirements.

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