Adapter plate process for sample testing electrical property of wafers

Abstract

The invention provides an adapter plate process for sample testing electrical property of wafers, comprising the following steps: manufacturing a needle clamp, setting probes on the needle clamp, manufacturing an adapter plate, setting front face electric connecting points on the front face of the adapter plate, setting TSV holes in the adapter plate through a TSV process, conducting the front face electric connecting points on the front face of the adapter plate to the back face; the front face electric connecting points on the front face of the adapter plate being mutually corresponding to the probes on the needle clamp; manufacturing a RDL re-wiring layer on the back face of the adapter plate, setting back face electric connecting points on the RDL re-wiring layer, each back face electric connecting point being in one-to-one correspondence with test points on to-be-tested wafers; bonding the surfaces of the to-be-tested wafers with the back face of the adapter plate through a temporary bonding process; choosing bonding adhesive with anisotropism conductive capacity and capable of conducting longitudinally and incapable of conducting transversely as the bonding adhesive, enabling the test points on the to-be-tested wafers to be in corresponding electric connection with the electric connecting points on the back face of the adapter plate; and inserting needles on the front face of the adapter plate. The adapter plate process can perform electrical performance test on the wafers with high-density test points.

Description

technical field [0001] The invention relates to the field of semiconductor packaging and testing, in particular to an adapter board process for wafer electrical random testing. Background technique [0002] With the popularity of electronic products in human society, wafer manufacturing and packaging have become more and more important industries. [0003] However, as the wafer manufacturing process becomes more and more advanced, the number of electrical test points on the wafer is also increasing and denser, especially when the process reaches below 28nm, the number of test pads per unit chip area is getting higher and higher. It is getting denser and denser, and the development of pin cards used for electrical testing has obviously been unable to keep up with the pace of wafer development. This is mainly because when the spacing between the pads reaches the order of nm, it is difficult to implant the pins on the pin card used for testing with traditional cantilever or ve...

AI Technical Summary

Problems solved by technology

[0003] However, as the wafer manufacturing process becomes more and more advanced, the number of electrical test points on the wafer is also increasing and denser, especially when the process reaches below 28nm, the number of test pads per unit chip area is getting higher and higher. The development of pin cards used for electrical testing has obviously been unable to keep up with the pace of wafer development.

This is mainly because when the spacing between the pads reaches the order of nm, it is difficult to implant the pins on the pin card used for testing with traditional cantilever or vertical pin cards, or they will also face electrical interference after implantation. Or the problem that the service life is too short

[0004] However, the testing of wafers is related to the reliability of subsequent packaging and device applications. Therefore, even if the test is more difficult, random testing is still necessary. Therefore, it is urgent to choose a process that can test the electrical properties of wafers.

[0005] Chinese patent application CN200810086130.6 discloses a wafer test method, which essentially uses the probe of the needle card to contact the pad for wafer testing. This patent application is mainly to solve the problem of dust particle pollution that may be caused during the test , but when the density of test points on the wafer is high, some of the above problems will still be faced

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