Sm and nanometer Mo contained chip-stacking interconnection material

Abstract

The invention discloses an Sm and nanometer Mo contained chip-stacking interconnection material, and belongs to the field of the chip interconnection material. The content of the rare earth element Sm in the interconnection material is 0.01-0.5%, the content of the nanometer Mo particles is 3-8%, and the balance is In. Firstly, In-Sm intermediate alloy powder is prepared by mechanical grinding; then the In-Sm powder, the In powder, mixed rosin resin, a thixotropic agent, a stabilizing agent, an active aid and an active agent are mixed and fully stirred; finally, the nanometer Mo particles are added and fully stirred to prepare paste-shaped Sm and nanometer Mo particles contained interconnection material; salient points are manufactured on the surface of the chip by adopting a jet printing process; and the chip perpendicular interconnection in a three-dimensional space is realized at a certain pressure of (1MPa-10MPa) and at the temperature of (170-260 DEG C) so as to form high-strength interconnection welding points. The interconnection material is high in reliability and can be used in three-dimensional packaged chip stacking.

Description

Technical field [0001] The invention relates to a chip stack interconnection material containing Sm and nano-Mo, and belongs to the field of chip interconnection materials. The interconnect material is mainly used in the fields of high reliability requirements for three-dimensional packaging, and is a new type of interconnect material with high performance. Background technique [0002] For the development of the electronics industry, Moore's Law has always been considered to guide the development direction of electronic device technology, but the increasing integration of a single chip seems to make it difficult to continue to use Moore's Law. The emergence of three-dimensional packaging chip stacking technology can greatly postpone the failure time of Moore's Law, so the electronics industry has also entered the post-Moore era. Three-dimensional packaging, that is, the vertical stacking of chips in a three-dimensional space, can achieve the dual effects of reducing chip size a...

AI Technical Summary

Problems solved by technology

However, intermetallic compounds also have their own disadvantages: (1) In the process of instantaneous liquid phase bonding, due to solid-liquid interdiffusion to form intermetallic compounds accompanied by volume shrinkage, there are obvious voids inside the solder joints, and the existence of voids will cause become the source of crack initiation during the service of solder joints; (2) during the service period, along with the "on-off" of electronic products, electronic devices are subjected to alternating temperature loads, because of the mismatch of linear expansion coefficients between packaging materials, solder The point is easy to become a stress concentration area, and when the stress value reaches a certain level, the solder joint will fail due to fatigue

The reliability of the three-dimensional packaging structure can be significantly improved by studying new interconnect materials, but there is currently a lack of relevant reports in the international community on research in this area

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