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Method, circuit and dram memory for improving input clock duty ratio immunity

A technology of input clock and duty cycle, which is applied in the field of DRAM memory to improve the immunity of input clock duty cycle, can solve the problems of abnormal control circuit function and clock loss, and achieve the effect of improving immunity

Active Publication Date: 2019-05-17
XI AN UNIIC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In order to solve the technical problems of clock loss or abnormal function of the control circuit in the existing clock path, the present invention provides a circuit and method for improving the immunity of the input clock duty cycle. The present invention can greatly improve the input clock duty cycle immunity

Method used

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  • Method, circuit and dram memory for improving input clock duty ratio immunity
  • Method, circuit and dram memory for improving input clock duty ratio immunity
  • Method, circuit and dram memory for improving input clock duty ratio immunity

Examples

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Embodiment Construction

[0036] Such as figure 2 As shown, the circuit for improving the immunity of the input clock duty cycle includes increasing the duty cycle circuit, reducing the duty cycle circuit and judging circuit, and increasing the duty cycle circuit is used to increase the duty cycle of the required clock Clk_G, Obtain increased duty cycle clock Clk_G+; reduce the duty cycle circuit to reduce the duty cycle of the required clock Clk_G to obtain a reduced duty cycle clock Clk_G-; the judgment circuit is used to determine the required clock Clk_G, increase Whether the duty cycle clock Clk_G+ and the reduced duty cycle clock Clk_G- are lost, and adjust the input clock receiver according to the judgment result.

[0037] Generally, increasing the duty cycle circuit includes adjusting the driving tube (it can be realized simply by adjusting the p / n ratio of the driving tube, p is strong and n is weak); reducing the duty cycle circuit includes adjusting the driving tube. It can be realized sim...

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Abstract

The invention relates to a circuit and method for improving the input clock duty ratio immunity and a DRAM. The circuit comprises a duty ratio increasing circuit, a duty ratio decreasing circuit and a judgment circuit. The duty ratio increasing circuit is used for increasing the duty ratio of a needed Clk_G to obtain a Clk_G+ with the increased duty ratio; the duty ratio decreasing circuit is used for decreasing the duty ratio of the needed Clk_G to obtain a Clk_G- with the decreased duty ratio; the judgment circuit is used for judging whether the Clk_G, the Clk_G+ with the increased duty ratio and the Clk_G- with the decreased duty ratio are lost or not and adjusting an input clock receiver according to a judgment result. The technical problem that a clock is lost or the function of a control circuit is abnormal in an existing clock path is solved, and the input clock duty ratio immunity can be greatly improved.

Description

technical field [0001] The invention belongs to the field of semiconductor chip design, and in particular relates to a circuit, a DRAM memory and a method for improving the duty ratio immunity of an input clock. Background technique [0002] Computers and various electronic devices are widely used in all aspects of modern life, and the demand for semiconductor chips is increasing. People's requirements for speed are getting faster and faster, and the chip clock is getting smaller and smaller. A slight disturbance of the clock provided by the system will cause a large change in the duty cycle of the input clock. And the change of the duty cycle of the input clock can easily lead to the malfunction of the chip. A design method proposed by the invention can greatly improve the immunity of the semiconductor chip to the duty cycle of the input clock and improve the reliability of the chip. figure 1 The basic architecture of a common semiconductor chip clock path, including inpu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/4063H03K3/017
Inventor 亚历山大
Owner XI AN UNIIC SEMICON CO LTD
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