Revising layout design through OPC to reduce corner rounding effect

Abstract

The present disclosure provides a method of fabricating a semiconductor device. A first layout design for a semiconductor device is received. The first layout design includes a plurality of gate lines and an active region that overlaps with the gate lines. The active region includes at least one angular corner that is disposed adjacent to at least one of the gate lines. The first layout design for the semiconductor device is revised via an optical proximity correction (OPC) process, thereby generating a second layout design that includes a revised active region with a revised corner that protrudes outward. Thereafter, the semiconductor device is fabricated based on the second layout design. The invention also relates to revising a layout design through OPC to reduce a corner rounding effect.

Description

[0001] Cross References to Related Applications [0002] This application is a continuation-in-part of U.S. Patent Application Serial No. 14 / 231,809, filed April 1, 2014, which is a continuation-in-part of U.S. Patent Application Serial No. 13 / 299,152, filed November 17, 2011 Divisional Patent Application of , both entitled "N / P Boundary Effect Reduction for Metal Gate Transistors," the entire contents of which are hereby incorporated by reference. technical field [0003] The present invention relates to modifying the layout design by OPC to reduce corner rounding effects. Background technique [0004] The semiconductor integrated circuit (IC) industry has experienced rapid development. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and producing ICs, so similar developments in IC processing and ...

AI Technical Summary

Problems solved by technology

However, conventional metal gate transistors may suffer from N / P boundary effects

In more detail, when a P-type metal gate transistor adjoins an N-type metal gate transistor, contamination may occur through metal diffusion across the boundary between the P-type and N-type metal gate transistors

This contamination can lower the threshold voltage (Vt) of metal gate transistors

Furthermore, as device dimensions continue to shrink, limitations in current lithography techniques may exacerbate the undesired Vt drift problem discussed above, further degrading the performance of conventional metal-gate transistors

[0006] Thus, while existing methods of fabricating metal gate transistors have been generally adequate for their intended purpose, they are not entirely satisfactory in every respect

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