RS code coder and coding method

Abstract

The invention discloses an RS code coder and a coding method. The RS code coder comprises an RS code parallel generation polynomial coefficient calculation module, an RS code symbol serial-parallel conversion module, an RS code parallel calculation enabling generation module and an RS code symbol parallel calculation module; the RS code parallel generation polynomial coefficient calculation module receives any RS code generation polynomial coefficient, completes parallel generation polynomial coefficient calculation, and transfers a parallel generation polynomial coefficient to the RS code symbol parallel calculation module; the RS code symbol serial-parallel conversion module completes serial-parallel conversion of input information to be coded, and outputs a parallel RS code information symbol; the calculation enabling generation module generates an enabling signal of the RS code parallel calculation module according to an input configuration parameter and a data clock; and the RS code symbol parallel calculation module completes parallel RS code check symbol calculation according to an RS code parallel generation polynomial coefficient and calculation enabling. The RS code coder and the coding method disclosed by the invention are applied to high-speed RS coding based on an FPGA high-speed modulator; and furthermore, self-adaptive coding of RS code rates defined in different finite fields can be supported.

Description

technical field [0001] The invention relates to an RS code encoder and an encoding method, belonging to the technical field of digital information transmission. Background technique [0002] In the forward error correction coding technology of the communication system, the RS (Reed-Solomon) code is a non-binary block cyclic code, which has a better ability to resist burst errors. When developing FPGA-based high-speed data modulators, RS codes are usually used to complete data channel coding to improve the effectiveness of information transmission. [0003] RS code is a kind of multi-ary BCH code, which is implemented by shift register structure, and its operations are all carried out on a given finite field. The operation mode of the finite field is determined by the field polynomial, and the generator polynomial is determined by the code length n and the information symbol length k of the RS code encoding. When the encoding rate is required to exceed the maximum serial pr...

AI Technical Summary

Problems solved by technology

If it is required to move in multiple RS code information symbols at a time, multiple multipliers or multiple look-up tables are required, and if the domain polynomial needs to be changed in real time (when the FPGA program is running), multiple look-up tables also need to be stored, which will take up More chip resources and limited flexibility

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