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Cell structure of VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) device and manufacturing method of cell structure

A manufacturing method and cell technology, which are applied in the manufacture of semiconductor/solid-state devices, semiconductor devices, electrical components, etc., can solve the problems of large on-resistance and large on-resistance of VDMOS devices, and achieve enhanced conduction capability and conduction. The effect of resistance reduction and production cost reduction

Active Publication Date: 2016-02-17
WUXI CHINA RESOURCES HUAJING MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In view of this, an embodiment of the present invention provides a cell structure of a VDMOS device and a manufacturing method thereof, so as to solve the problem that the on-resistance of the JFET region in the cell structure of the VDMOS device in the prior art is large so that the VDMOS device is turned on. Technical problem with large resistance

Method used

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  • Cell structure of VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) device and manufacturing method of cell structure
  • Cell structure of VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) device and manufacturing method of cell structure
  • Cell structure of VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) device and manufacturing method of cell structure

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Embodiment 1

[0040] The first embodiment of the present invention provides a cell structure of a VDMOS device. figure 2 It is a structural diagram of the cell structure of a VDMOS device according to the first embodiment of the present invention. Such as figure 2 As shown, the cell structure of the VDMOS device includes: a drain region 21; an N-epitaxial layer 22 on the drain region 21; a P-well region 23 on the N-epitaxial layer 22; The P-well region 23 and the N-type first region 24 in the N-epitaxial layer 22, wherein the N-type first region 24 penetrates the P-well region 23 in the longitudinal direction and is connected to the N- The epitaxial layer 22 is connected; the gate structure 25 located on the P-well region 23; and the N+ source region 26 located in the P-well region 23.

[0041] It should be noted that the N-type first region 24 penetrates the "longitudinal" in the P-well region 23 in the longitudinal direction. figure 2 Middle is the direction from the P-well region 23 to t...

Embodiment 2

[0049] The second embodiment of the present invention provides a method for manufacturing a cell structure of a VDMOS device. image 3 It is a flow chart of the manufacturing method of the cell structure of the VDMOS device in the second embodiment of the present invention. Such as image 3 As shown, the manufacturing method of the cell structure of the VDMOS device includes:

[0050] S301: Provide a semiconductor material including a drain region and an N-epitaxial layer formed on the drain region.

[0051] In this step, by providing a semiconductor material including a drain region and an N-epitaxial layer formed on the drain region, it can provide a basis for the subsequent formation of other parts of the cell structure of the VDMOS device.

[0052] S302, forming a P-well region on the N-epitaxial layer.

[0053] Specifically, a P-well region is formed on the N-epitaxial layer by light doping with P-type ions. Moreover, the doping concentration of the P-well region can be adjust...

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Abstract

The invention discloses a cell structure of a VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) device and a manufacturing method of the cell structure. The cell structure comprises a drain region, an epitaxial layer of a first conductivity type, a well region of a second conductivity type, a first region of the first conductivity type, a gate structure and a source region of the first conductivity type, and is characterized in that the epitaxial layer is located on the drain region; the well region is located on the epitaxial layer; the first region is located in the well region and the epitaxial layer, wherein the first region penetrates through the well region along the longitudinal direction and is connected with the epitaxial layer; the gate structure is located on the well region; and the source region is located in the well region. The cell structure disclosed by the invention can enable the doping depth of the first region to be deeper and enable the doping concentration to be higher, so that conduction resistance of the cell structure can be enabled to be reduced, thus conduction resistance of the corresponding VDMOS device is also enabled to be reduced, and the unit area current conduction capability is enhanced. Therefore, the area of the VDMOS device can be enabled to be reduced under the condition of reaching the same conduction current, so that the production cost of the VDMOS device can be reduced.

Description

Technical field [0001] The embodiment of the present invention relates to the field of semiconductor technology, in particular to a cell structure of a VDMOS device and a manufacturing method thereof. Background technique [0002] VDMOS (VerticalDouble-diffusedMetalOxideSemiconductor, vertical double-diffused metal oxide semiconductor) devices, among many power semiconductor devices, have the advantages of bipolar transistors and ordinary MOS devices. Compared with bipolar transistors, it has fast switching speed, low switching loss, high input impedance, low driving power, good frequency characteristics, high transconductivity, no secondary breakdown problem of bipolar power devices, and safety Large working area. Therefore, VDMOS devices are ideal power semiconductor devices regardless of switching applications or linear applications. [0003] For VDMOS devices, one of its important indicators is on-resistance. With the development of VDMOS devices, their structure has been co...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/06H01L21/336
Inventor 魏峰张新
Owner WUXI CHINA RESOURCES HUAJING MICROELECTRONICS
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