LDMOS-SCR device with source-end embedded finger NMOS

Abstract

The invention provides an LDMOS-SCR device with a source-end embedded finger NMOS, which can be applied to improving ESD protection reliability of an on-chip IC. The LDMOS-SCR device with the source-end embedded finger NMOS mainly comprises a P substrate, a P epitaxy, a P well, an N well, a first N+ injection region, a second N+ injection region, a first P+ injection region, a third N+ injection region, a fourth N+ injection region, a second P+ injection region, a fifth N+ injection region, a plurality of polysilicon gates, a plurality of thin gate oxides and a plurality of field oxide insulation regions. On one hand, the second P+ injection region, a third polysilicon gate, the fifth N+ injection region, the N well, the P well, the first P+ injection region, the first N+ injection region form a parasitical LDMOS-SCR current path, thereby reinforcing the ESD robustness of the LDMOS-SCR device; on the other hand, the first N+ injection region, a first polysilicon gate, a first thin gate oxide, the second N+ injection region, the first P+ injection region, the third N+ injection region, a second polysilicon gate, a second thin gate oxide and the fourth N+ injection region form the finger NMOS and a parasitic resistor, thereby forming a resistance-capacitance coupling effect; thereby, the maintaining voltage is increased.

Description

technical field [0001] The invention belongs to the field of electrostatic discharge protection of integrated circuits and relates to an ESD protection device, in particular to an ESD protection device with an LDMOS-SCR embedded with interdigitated NMOS at the source end, which can be used to improve the reliability of ESD protection of ICs on a chip . Background technique [0002] ESD (electrostatic discharge) is one of the important factors affecting the reliability of today's IC. Circuit dysfunction or gate oxide breakdown damage caused by ESD to ICs has attracted widespread attention in the industry. The damage phenomenon caused by ESD in IC is mainly manifested in the following aspects: dielectric breakdown caused by ESD in the semiconductor device, resulting in rupture of the oxide film; local overheating of the internal circuit caused by EOS (electrical overstress) or ESD in the IC, Lead to the melting of metal wires; in ESD protection devices, due to the low voltag...

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Problems solved by technology

[0004] In view of the common problems of low maintenance voltage and insufficient anti-latch-up ability of the existing ESD protection devices with SCR structure, the present invention designs an LDMOS-SCR device with interdigitated NMOS embedded in the source end, which not only makes full use of the SCR The device is characterized by strong robustness, and the resistance-capacitance coupling effect formed by the increased N+ implantation region at the source of the device, the polysilicon gate and the thin gate oxide layer is used to improve the maintenance voltage of the ESD protection design scheme and enhance the ESD robustness of the device sex

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