Semiconductor layer structure and preparation method thereof and thin-film transistor
A technology of thin film transistors and semiconductors, applied in the direction of transistors, semiconductor devices, electric solid devices, etc., can solve problems such as reducing electron mobility, achieve the effect of increasing charging speed, reducing resistance, and ensuring normal operation
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no. 1 approach
[0019] see figure 1 , the semiconductor layer structure 10 provided by the embodiment of the present invention is an essential part of a thin film transistor. The semiconductor layer structure 10 includes an insulating substrate 12 , a buffer layer 14 and a semiconductor layer 16 . The insulating substrate 12 can be a glass substrate. The buffer layer 14 and the semiconductor layer 16 are sequentially pasted on the insulating substrate 12, and the buffer layer 14 is located between the semiconductor layer 16 and the insulating substrate 12, in other words, the buffer layer 14 is pasted on both sides with The semiconductor layer 16 and the insulating substrate 12 .
[0020] see figure 2 , the semiconductor layer 16 includes a source signal access terminal 160 , a drain signal access terminal 161 , a first semiconductor layer pattern 162 , and a second semiconductor layer pattern 164 . The source signal access terminal 160 and the drain signal access terminal 161 are spaced...
no. 2 approach
[0024] Please also refer to figure 1 and figure 2 According to an embodiment of the present invention, a method for preparing a semiconductor layer structure includes the following steps:
[0025] An insulating substrate 12 is provided, which may be a glass substrate.
[0026] A buffer layer 14 is formed on the insulating substrate 12 .
[0027] A semiconductor layer 16 is formed on the buffer layer 14 . Specifically, the semiconductor layer 16 includes a source signal access terminal 160 , a drain signal access terminal 161 , a first semiconductor layer pattern 162 , and a second semiconductor layer pattern 164 . The source signal access terminal 160 and the drain signal access terminal 161 are spaced apart on the buffer layer 14 . Both the first semiconductor layer pattern 162 and the second semiconductor layer pattern 164 are “n” shaped and straddle between the source signal access terminal 160 and the drain signal access terminal 161 . Specifically, the first semicon...
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