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A designing method of low-consumption SRAM chip bit lines and a circuit structure

A design method and circuit structure technology, applied in information storage, static memory, digital memory information and other directions to achieve the effect of reducing power consumption and reducing overall power consumption

Active Publication Date: 2016-03-30
GUSHAN ELECTRONICS SCI & TECH SHANGHAI CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Similarly, the capacitance and resistance of the word line in the SRAM array is also very large, which is also the main consumer of power consumption. However, only one word line is flipped in a write operation, and a 32-bit SRAM will have 32 bits in a write operation. line flipped
As far as the bit line itself is concerned, the power consumption of a single write operation is greater than the power consumption of a read operation.

Method used

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  • A designing method of low-consumption SRAM chip bit lines and a circuit structure
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  • A designing method of low-consumption SRAM chip bit lines and a circuit structure

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Embodiment Construction

[0030] The design method and circuit structure of the charge pump technology applied to the bit line of the SRAM chip proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[0031] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0032] Aiming at the bit line of the SRAM during write operation, the invention proposes a method of collecting the bit line charges by using the charge pump principle and generating high voltage to transfer the charges back to the bit line.

[0033] The pre...

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Abstract

The invention relates to a designing method of low-consumption SRAM chip bit lines and a circuit structure. The designing method includes 1) connecting the SRAM chip bit lines to a charge pump circuit, 2) firstly collecting charges to be discharged on the bit lines to a plurality of capacitors of a charge pump during write operation, and 3) allowing the charge pump circuit to obtain a high voltage by utilization of a working principle of the charge pump, and transferring the charges collected by the charge pump to the bit lines. Compared with the prior art, the designing method and the circuit structure are advantaged by saving power consumption.

Description

technical field [0001] The invention relates to a design method for reducing the charge and discharge power consumption of bit lines in a low-power SRAM chip. Capacitors are used to collect the charges on the bit lines of the SRAM chip, and then the collected charges are re-transferred to the bit lines by using the principle of a charge pump to reduce bit lines. The power consumption of line charging and discharging. Background technique [0002] SRAM is the abbreviation of StaticRAM in English, that is, Static Random Access Memory (Static Random Access Memory). It has the function of static access, which can save the data stored inside without refreshing the circuit. And DRAM, DRAM (Dynamic Random Access Memory) needs to be refreshed and charged every once in a while, otherwise the internal data will disappear, so SRAM has high performance, but SRAM also has its disadvantages, that is, its integration is low. DRAM memory with the same capacity can be designed to be smalle...

Claims

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Application Information

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IPC IPC(8): G11C11/413
Inventor 王旭吕超
Owner GUSHAN ELECTRONICS SCI & TECH SHANGHAI CO LTD
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