ROM memory cell, memory array, memory and reading method

Abstract

The present invention relates to a ROM memory cell, a memory array, a memory and a reading method. The ROM memory cell comprises at least a CG-FinFET transistor (Fin Field-Effect Transistor) and / or an IG-FinFET transistor. The information storage density of the ROM memory cell can be improved.

Description

technical field [0001] The invention relates to an integrated circuit, in particular to a ROM storage unit, a storage array, a memory and a reading method. Background technique [0002] In integrated circuit design, for memory, it is the trend to increase storage density, reduce unit information storage cost, and reduce chip area. Under process conditions such as 40nm and below, due to the limitation of process rules, the area of ​​ROM storage unit cannot be reduced proportionally with the process size, and the storage area of ​​unit information is not satisfactory. [0003] The transistors in a traditional ROM memory cell share a source and the source is commonly connected to the ground voltage VSS, such as figure 1 What is shown is a schematic diagram of the circuit structure of a traditional ROM storage unit. It includes: NMOS transistor MOS11, and NMOS transistor MOS12. The sources of these two NMOS transistors are connected to the ground voltage VSS, the drains of th...

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Problems solved by technology

[0012] However, the above-mentioned ROM storage units of the current technology can only store one bit of storage information, and the storage density is very low, which cannot further reduce the chip area of ​​the memory.

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