Method for forming semiconductor device

Abstract

The invention provides a method for forming a semiconductor device, comprising the following steps: forming a first dielectric layer on a substrate, and forming a barrier layer on the first dielectric layer; etching the barrier layer and the first dielectric layer to form first through holes which expose the source or drain of a first transistor on the substrate; and after a first conductive layer filling the first through holes is formed, adopting a planarization process to remove the first conductive layer on the barrier layer, and forming first conductive plugs in the first through holes. In the planarization process, the barrier layer as a stop layer can avoid damage to the first dielectric layer and avoid the problem that an apparent 'dishing structure' is formed on the surface of the first dielectric layer due to the damage to the first dielectric layer, thus improving the performance of the formed semiconductor device.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a semiconductor device. Background technique [0002] With the development of semiconductor technology, the integration level of semiconductor devices continues to increase, and the feature size (Critical Dimension, CD) of semiconductor devices becomes smaller and smaller. [0003] In order to improve the integration of semiconductor devices, the semiconductor elements on a semiconductor wafer have a multi-layer structure. The connection structure realizes electrical connection. [0004] Figure 1 ~ Figure 4 A structural schematic diagram of a specific example for the formation process of the existing interconnection structure, including: [0005] first reference figure 1 , forming semiconductor elements such as a plurality of transistors 11, 12 on the substrate 10 (it is worth noting that the functions of the transistor 11 and the transistor 12 ar...

AI Technical Summary

Problems solved by technology

However, the performance of the semiconductor device after the interconnection structure formed by the above process is poor, and cannot meet the development requirements of semiconductor devices

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