[0045] As mentioned in the background technology, the performance of the semiconductor device after the interconnection structure formed by the existing process cannot meet the needs, and the reason is analyzed: combined with reference Figure 1 to Figure 6.
[0046] In the formation process of the existing interconnect structure, a first through hole 15 is formed in the first dielectric layer 14, and a first metal layer filling the first through hole 15 is formed on the first dielectric layer 14 After 16 , CMP is used to remove the redundant first metal layer 16 on the first dielectric layer 14 , so as to form a first conductive plug 17 in the first through hole 15 . Wherein, in the CMP process, after the polishing pad removes the first metal layer 16 on the first dielectric layer 14, it is also easy to remove the first dielectric layer 14 with a partial thickness, but the grinding rate based on the first conductive plug 17 is much lower than that of the first dielectric layer 14. The grinding rate much lower than that of the first dielectric layer 14 and the deformation of the grinding pad will cause local differences in the grinding of the first dielectric layer 14 .
[0047] like Figure 5 As shown, after the CMP process, a "dish structure" (disshing) 23 is formed on the surface of the first dielectric layer 14, so that the thickness of the dielectric layer 14 above the transistor 12 (that is, the first conductive plug 17 is not formed) is much higher than that of the first dielectric layer 14. The thickness is smaller than the thickness of the dielectric layer 14 above the transistor 11 (that is, the first conductive plug 17 is formed), thereby affecting the performance of the subsequently formed semiconductor device.
[0048] as reference Image 6 As shown, even if the barrier layer 18 is formed above the first dielectric layer 141 subsequently, the second dielectric layer 20 is formed on the barrier layer 18; and then the second dielectric layer 20 is etched to form the second through hole and the second through hole. After three through holes, a second plug is formed in the second through hole and a third conductive plug 25 is formed in the third through hole. Due to the existence of the dish structure 23, the third conductive plug 25 and the semiconductor element (such as the transistor 11) in the first dielectric layer 14 is reduced, and thus lead to increase the capacitance between the third conductive plug 25 and the transistor 11, reducing the subsequent formation of the semiconductor device performance.
[0049] Especially with the development of semiconductor technology, the size of semiconductor elements decreases, the ratio of the thickness of the dielectric layer between semiconductor elements to the size of the semiconductor element increases, and in order to reduce the RC delay effect between the interconnection structures in the dielectric layer, the dielectric layer is mostly sparsely structured Low K dielectric material. The low-K dielectric material is ground at a faster rate, so the above-mentioned thickness difference between different regions on the surface of the first dielectric layer 14 is more obvious, that is, the defect of "disk structure" is more obvious. The impact on subsequent semiconductor devices is more serious.
[0050] To this end, the present invention provides a method for forming a semiconductor device. A first transistor is formed on a substrate, and then a first dielectric layer covering the first transistor is formed on the substrate, and then on the first dielectric layer Form a barrier layer; etch the barrier layer and the first dielectric layer to form a first through hole, the first through hole exposes the source or drain of the first transistor; and fill the first through hole after forming And after covering the first conductive layer of the barrier layer, using the barrier layer as a stop layer, a planarization process is used to remove the first conductive layer on the barrier layer, thereby forming a first guide plug in the first through hole stuffed. Wherein, in the planarization process, the barrier layer is used as a stop layer, so as to prevent the first dielectric layer under the barrier layer from being damaged, thereby avoiding that in the planarization process, the etch rate based on the first conductive plug is lower than that of the first conductive plug. The etch rate of a dielectric layer, resulting in the defect that the etch rate of the first dielectric layer in the part not provided with the first conductive plug is obviously greater than that of the first dielectric layer provided with the first conductive plug part, and thus An obvious "disk structure" defect is formed on the surface of the first dielectric layer, thereby reducing adverse effects on the subsequent manufacturing steps of the semiconductor device and improving the performance of the final formed semiconductor device.
[0051] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.
[0052] Figure 7 to Figure 14 A schematic structural view of an embodiment of a method for forming a semiconductor device of the present invention.
[0053] The method for forming a semiconductor device provided in this embodiment includes:
[0054] refer to Figure 7 As shown, a substrate 30 is provided on which transistors are formed.
[0055] In this embodiment, the transistors include a first transistor 31 and a second transistor 32 .
[0056] In this embodiment, the first transistor 31 and the second transistor 32 are CMOS transistors. Taking the first transistor 31 as an example, they include a gate (not shown in the figure), and sources located on both sides of the gate. Pole or drain 33 and other structures. Forming the first transistor 31 and the second transistor 32 is a mature technology in the field, and will not be repeated here. However, it should be noted that in this embodiment, the first transistor 31 and the second transistor 32 have different functions, and the source or drain of the first transistor 31 needs to be directly electrically connected to the upper semiconductor element subsequently, while the second transistor 32 does not need to be directly electrically connected to the upper semiconductor element.
[0057] In this embodiment, the base 30 includes: a semiconductor substrate. Or a semiconductor substrate and a semiconductor element structure such as an interconnection structure located within the semiconductor substrate.
[0058] The semiconductor substrate is a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a glass substrate or other III-V compound substrates . The material and structure of the semiconductor substrate do not limit the protection scope of the present invention.
[0059] refer to Figure 8 , forming a first dielectric layer 34 on the substrate 30 , the first dielectric layer 34 covers the first transistor 31 and the second transistor 32 .
[0060] The first dielectric layer 34 is a dielectric material for forming an interconnection structure.
[0061] In this embodiment, the first dielectric layer 34 is silicon oxide, and the formation process is chemical vapor deposition (Chemical Vapor Deposition, CVD). However, the material of the first dielectric layer 34 is not limited to silicon oxide, and the formation process is not limited to CVD. Dielectric layer materials and formation processes in the art are applicable to this embodiment.
[0062] Afterwards, a barrier layer 35 is formed on the first dielectric layer 34 . In this embodiment, the polishing rate of the barrier layer 35 in the subsequent planarization process is smaller than that of the first dielectric layer 34 .
[0063] The material of the barrier layer 35 includes silicon nitride (SiN), silicon carbide (SiC) or silicon oxynitride (SiON) and the like. The formation process includes chemical vapor deposition (CVD) and atomic layer deposition (ALD).
[0064] In this embodiment, the barrier layer 35 is made of silicon nitride.
[0065] After the barrier layer 35 is formed, the barrier layer 35 and the first dielectric layer 34 can be etched to form conductive plugs.
[0066] In this embodiment, before the blocking layer 35 is etched, the third dielectric layer 36 is formed on the blocking layer 35 first.
[0067] In this embodiment, the material of the third dielectric layer 36 is a dielectric material. Optionally, the material of the third dielectric layer 36 is the same as that of the first dielectric layer 36 (silicon oxide). for CVD. However, in the present invention, the material and formation process of the third dielectric layer 36 are not limited.
[0068] Then refer to Figure 9 , etch the third dielectric layer 36, the barrier layer 35 and the first dielectric layer 34, and form a first through hole 37 in the third dielectric layer 36, the barrier layer 35 and the first dielectric layer 34 , the first through hole 37 exposes the source or drain 33 of the first transistor 31 .
[0069] The specific process includes: first forming a first hard mask 50 on the third dielectric layer 36, and then sequentially etching the third dielectric layer 36, barrier layer 35 and The first dielectric layer 34 is used to form the first through hole 37 . The process of etching the third dielectric layer 36 , the barrier layer 35 and the first dielectric layer 34 is a mature process in the field and will not be repeated here.
[0070] Optionally, after forming the first through hole 37, a diffusion barrier layer (not shown) is formed on the sidewall of the first through hole 37, and the material of the diffusion barrier layer may be tantalum (Ta ), tantalum nitride (TaN) or titanium nitride (TiN), etc. The formation process is CVD or PVD, etc., and the diffusion barrier layer is a mature technology in the field, and will not be repeated here.
[0071] The diffusion barrier layer can effectively inhibit the subsequent formation and diffusion of atoms in the conductive plugs in the first through hole into the first dielectric layer, thereby improving the performance of the subsequently formed semiconductor device, but does not form the diffusion The barrier layer does not prevent the realization of the object of the present invention.
[0072] refer to Figure 10 filling the first through hole 37 with a first conductive material to form a first conductive layer 38 filling the first through hole 37 and covering the barrier layer 35 .
[0073] In this embodiment, the first conductive material is tungsten (W), and the formation process is physical vapor deposition (Physical Vapor Deposition, PVD).
[0074] combined reference Figure 11 , using the barrier layer 35 as a stop layer, using a planarization process to remove the first conductive layer 38 on the third dielectric layer 36, exposing the first conductive layer in the first through hole 37, so that the A first conductive plug 39 is formed in the third dielectric layer 36 , the barrier layer 35 and the first dielectric layer 34 .
[0075] In this embodiment, the upper end of the first conductive plug 39 is exposed from the barrier layer 35 . Moreover, the first conductive plug 39 can slow down the grinding rate of the third dielectric layer 36 , so as to relieve the grinding pressure of the barrier layer 35 and reduce the risk of the barrier layer 35 being ground completely.
[0076] In this embodiment, the planarization process is CMP, wherein, during the CMP process, the grinding rate of the barrier layer 35 is lower than that of the third dielectric layer 36 .
[0077] continue to refer Figure 11 After removing all the first conductive layer on the third dielectric layer 36 , it is easy to grind and remove part of the thickness of the third dielectric layer 36 and part of the first conductive plug 39 located in the first through hole 37 . However, based on this embodiment, the material of the first conductive plug 39 is metal tungsten, the material of the third dielectric layer 36 is silicon oxide, and the grinding rate of the third dielectric layer 36 is obviously higher than that of the first conductive plug. The grinding rate of the plug 39, the first conductive plug 39 slows down the grinding rate of the third dielectric layer 36 where it is located; The grinding rate of the third dielectric layer 36 at the plug 39 is significantly faster, so that a "dish" 231 is formed on said third dielectric layer 36 .
[0078] However, in this embodiment, the barrier layer 35 is used as a stop layer. After the third dielectric layer 36 on the barrier layer 35 is removed, the barrier layer 35 eases the grinding rate of CMP, thereby avoiding further grinding of the The first dielectric layer 34 can further reduce damage to the first dielectric layer 34 and improve the window of the CMP process.
[0079] If the thickness of the barrier layer 35 is too large, it will affect the overall size of the semiconductor device formed subsequently; and in the CMP process, the barrier layer 35 will also be consumed, if the thickness of the barrier layer 35 is too small, the barrier layer 35 is completely ground, thereby causing damage to the first dielectric layer 34 below it.
[0080] In this embodiment, the thickness of the barrier layer 35 is
[0081] refer to Figure 12 , forming a second dielectric layer 40 on the third dielectric layer 39 .
[0082] In this embodiment, the material of the second dielectric layer 40 is also a dielectric material. Optionally, the material of the second dielectric layer 40 is the same as that of the first dielectric layer 34 , which is silicon oxide. The forming process is CVD, but the material and forming process of the second dielectric layer 40 do not limit the protection scope of the present invention.
[0083] refer to Figure 13 , forming a second hard mask 51 on the second dielectric layer 40, using the second hard mask 51 as a mask, and using the barrier layer 35 as an etch barrier to etch the second dielectric Layer 40 forms a second via 41 , and a third via 42 .
[0084] During the etching process of the second dielectric layer 40 , the etching rate of the barrier layer 35 is lower than the etching rate of the second dielectric layer 40 .
[0085] And the etching rate of the first conductive plug 39 is much lower than the etching rate of the second dielectric layer 40 .
[0086] The second through hole 41 exposes the first conductive plug 39 , and the third through hole 42 is located above the second transistor 32 and exposes the barrier layer 35 .
[0087] In this embodiment, the process of etching the second dielectric layer 40 is dry etching. The process of dry etching the second dielectric layer 40 is a mature technology in the field, and will not be repeated here.
[0088] combined reference Figure 14 , filling the second through hole 41 and the third through hole 42 with a second conductive material, forming a second conductive plug 43 in the second through hole 41, forming a first conductive plug in the third through hole 42 Three conductive plugs 44 . The second conductive plug 43 is electrically connected to the first conductive plug 39 , and the third conductive plug 44 is separated from the second transistor 12 .
[0089] In this embodiment, the second conductive material is copper (Cu). However, the present invention is not limited to the specific material of the second conductive material.
[0090] In this embodiment, the barrier layer 35 can reduce the damage of the first dielectric layer 34 in the above CMP process, resulting in a reduction in the thickness of the first dielectric layer 34 on the second transistor 12, thereby avoiding The local thickness reduction of the first dielectric layer 34 causes the distance between the second transistor 12 and the third conductive plug 44 to decrease, and solves the problem of increasing the distance between the second transistor 12 and the third conductive plug 44 caused by this. The capacitance between the plugs 44 further affects the performance of the subsequently formed semiconductor device. In addition, in the process of etching the second dielectric layer 40, using the barrier layer 35 as an etching barrier layer can effectively control the etching end point of etching the second dielectric layer 40, avoiding the The damaged layer 34 further effectively controls the distance between the third conductive plug 44 and the second transistor 12 , and at the same time reduces the difficulty of the process and increases the process window.
[0091] It is worth noting that, combined with reference Figure 9 and Figure 10 , in this embodiment, after forming the barrier layer 35, a third dielectric layer 36 is formed on the barrier layer 35, and then the third dielectric layer 36, the barrier layer 35 and the first dielectric layer 34 are etched to form The first through hole is filled with a first conductive material to form the first conductive plug 39 , and the upper end of the first conductive plug 39 is exposed above the barrier layer 35 . In another embodiment of the present invention, after the barrier layer 35 is formed on the first dielectric layer 34, there is no need to form the third dielectric layer 36, but the barrier layer 35 and the first dielectric layer are directly etched. 34 to form a first through hole. After the subsequent formation of the first conductive layer, the barrier layer 35 is directly used as a stop layer, and the redundant first conductive layer is removed to form a first conductive plug, and the surface of the first conductive plug is flush with the surface of the barrier layer . The above process reduces process steps and improves process efficiency.
[0092] Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.
