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Patterning Methods and Semiconductor Structures

A patterning and patterning technology, applied in semiconductor/solid-state device manufacturing, photoengraving process of patterned surface, original for optomechanical processing, etc. and other problems, to achieve the effect of improving the uniformity of critical dimensions, high uniformity of critical dimensions, and improving the problem of misalignment

Active Publication Date: 2018-07-13
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the pattern made in this way may be misaligned, and due to the difficulty in process, it is also difficult to control the critical dimension uniformity.

Method used

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  • Patterning Methods and Semiconductor Structures
  • Patterning Methods and Semiconductor Structures
  • Patterning Methods and Semiconductor Structures

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0055] Figure 1A to Figure 1E It is a top view of the flow of the patterning method according to the embodiment of the present invention. Figure 2A to Figure 2E is to draw Figure 1A to Figure 1E Schematic cross-sectional view of tangent line A-A'. Figure 3A to Figure 3E is to draw Figure 1A to Figure 1E Schematic sectional view of tangent line B-B'.

[0056] Please refer to Figure 1A to Figure 3A, providing a substrate 10 and forming a material layer 12 on the substrate 10 . The substrate 10 is, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor over insulator (SOI) substrate. Semiconductors are, for example, atoms of group IVA, such as silicon or germanium. The semiconductor compound is, for example, a semiconductor compound formed of atoms of group IVA, such as silicon carbide or germanium silicide, or a semiconductor compound formed of atoms of group IIIA and group VA, such as gallium arsenide. The material layer 12 is, ...

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Abstract

The invention discloses a patterning method, which includes: providing a substrate with a material layer; forming a patterned hard mask layer on the material layer, which has a plurality of first holes; then, forming a mask layer, It includes a plurality of line pattern masks, the line pattern masks extend along a direction, and each first hole is separated into a second hole and a third hole; a patterned hard mask layer and a mask layer are used as The mask is used to pattern the material layer to form a patterned material layer with a plurality of fourth holes and fifth holes. The invention also provides a semiconductor structure.

Description

technical field [0001] The present invention relates to an integrated circuit, and more particularly to a patterning method and semiconductor structure. Background technique [0002] Known photolithography techniques such as ArF immersion lithography can only produce a pitch of about 76nm in a single process. To make a smaller pitch, a secondary photolithography and secondary etching process is required. However, the pattern made in this way may have misalignment, and due to the difficulty in process, it is also difficult to control the critical dimension uniformity. Therefore, there is an urgent need in the industry for a method that can be implemented using the existing photolithography process, but can also obtain a smaller pattern pitch. Contents of the invention [0003] The invention provides a patterning method, which can obtain smaller pattern spacing and critical dimensions, and align the produced patterns with each other, improve the problem of misalignment, and...

Claims

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Application Information

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IPC IPC(8): H01L21/027G03F1/76
Inventor 杨金成
Owner MACRONIX INT CO LTD