Method for forming grid through employing dual graphic technology
A double patterning and technical technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problem of low alignment accuracy of the double patterning process, and achieve improved alignment accuracy, performance and yield, and high sensitivity. Effect
Active Publication Date: 2016-04-13
SEMICON MFG INT (SHANGHAI) CORP +1
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[0006] The purpose of this application is to provide a method for forming a gate using double patterning technology to solve the problem of low alignment accuracy of the double patterning process in the prior art
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[0033] It should be pointed out that the following detailed description is exemplary and intended to provide further explanation to the present application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
[0034] It should be noted that the terminology used here is only for describing specific implementations, and is not intended to limit the exemplary implementations according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should also be understood that when the terms "comprising" and / or "comprising" are used in this specification, it indicates There are features, steps, operations, means, components and / or combinations thereof.
[0035] For the convenience of description, spatially relative terms may be used here...
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The invention provides a method for forming a grid through employing the dual graphic technology. The method comprises the steps: S1, sequentially setting a gate oxide layer, a first polycrystalline silicon layer and a gate medium layer on a semiconductor substrate; S2, carrying out the first photoetching and the first etching, and forming a first groove in the gate medium layer; S3, carrying out the second photoetching and the second etching, and forming a second groove in the gate medium layer; S4, carrying out the etching of the first polycrystalline silicon layer and the gate oxide layer along the side walls of the first and second grooves, and forming the grid, wherein the gate medium layer comprises a second polycrystalline silicon layer. The polycrystalline silicon in the gate medium layer is more sensitive to light, so a strong light signal provided by the second polycrystalline silicon layer exposed at the first groove is used for achieving the improvement of the alignment precision of the second photoetching, thereby achieving the better control of the uniformity of a key size, enabling the key sizes formed through the first and second etching technology, and facilitating the improvement of the performance and yield of products.
Description
technical field [0001] The present application relates to the technical field of semiconductor manufacturing, and in particular, relates to a method for forming a gate using a double patterning technique. Background technique [0002] At present, at the technology node of 32nm and below, it is applied to the key-level lithography process. Since the resolution index required by it has exceeded the limit capability of the existing optical lithography platform, the industry has adopted a variety of technical solutions to solve the problem. For this technical problem, the application of dual graphics technology is relatively extensive. [0003] According to the results of technical research, lithography-etch-litho-etch (litho-etch-litho-etch for short LELE) technology is one of the mainstream technologies of several dual patterning at present, that is, through two separate photolithography and etching The target pattern is formed by etching, and the target pattern can include t...
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IPC IPC(8): H01L21/28H01L21/027
Inventor 刘畅韩秋华
Owner SEMICON MFG INT (SHANGHAI) CORP