FPGA-based accelerator card and acceleration method thereof

Abstract

The present invention provides an acceleration method of an FPGA-based accelerator card. The acceleration method comprises the following process of constructing a PCI-E bus interface module, a plurality of DMAs, a DMA reset module, a plurality of user-reconfigurable acceleration modules, an LVDS-optical fiber module, a crossed bus module and DDR3 control modules in an FPGA. The present invention also provides an accelerator card obtained by utilization of the acceleration method. The FPGA-based accelerator card and the acceleration method thereof are simple in implementation method and low in cost; the plurality of DMAs and the plurality of user-reconfigurable acceleration modules are configured, processing time is saved by decomposing the task and performing parallel computing, and processing efficiency is improved; a plurality of accelerator cards can be crossed through LVDS and optical fiber and can be freely expanded according to application requirements; and by utilization of the reconfigurable characteristics of the FPGA, different acceleration applications can be achieved by loading different bit steam files, and application range is wide.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to an FPGA-based acceleration card and an acceleration method thereof. Background technique [0002] FPGA (Field-Programmable Gate Array), that is, field programmable gate array, is the product of the development of programmable devices such as PAL, GAL, and CPLD. The device was first launched by Xilinx in 1985. It is a new type of high-density PLD, which is made by CMOS-SRAM technology. The structure of FPGA is divided into three parts: programmable logic module, programmable I / O module and programmable internal interconnection area IR. There are many programmable logic units (LE, LogicElement) inside the FPGA. Users can program these programmable modules on-site to achieve different logic functions. Compared with application-specific integrated circuits, FPAG has higher flexibility and development The cycle is shorter and the single integration is lower. FPGA can be programme...

AI Technical Summary

Problems solved by technology

Using hardware acceleration such as FPGA chips to share part of the CPU work is the current mainstream solution, but there are two problems with using FPGA for hardware acceleration. One is that the resources of an FPGA accelerator are not enough to solve some complex and large-scale calculation tasks; the other is When using FPGA for co-processing and running multiple acceleration algorithms at the same time, under the same PCI-E interface, several devices coexist, and the hardware driver may be quite troublesome.

[0005] After searching, it was found that the Chinese patent application with the publication number CN102819818A provides a method for realizing image processing based on the dynamic reconfigurable technology of the FPGA chip, using the reconfigurable technology of the FPGA chip to realize the acceleration of image processing, and generating image processing Design files of the functional modules, and then configure the reconstruction module of the FPGA chip as one or more image processing functional modules for image signal processing; this method is simple to implement and low in cost, but requires pre-generated fixed image processing functions Module with limited scope of application and limited to image processing functions

The Chinese patent application with the publication number CN104657308A provides a method of server hardware acceleration implemented by FPGA, based on FPGA-based server hardware acceleration using QPI bus, by building a hardware acceleration module in the FPGA, and through the message conversion module The operation initiated by the hardware acceleration module is converted into a message and sent to the QPI bus for acceleration; this method can be configured with different acceleration algorithms to correspond to different computing applications. Although it has high flexibility and scalability, it is only applicable to the QPI bus The computer is not universal and universal to the mainstream PCI-E bus

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