Fan-out type 3D packaging structure embedded in silicon substrate

Abstract

The invention discloses a fan-out type 3D packaging structure embedded in a silicon substrate. In the packaging structure, a functional chip is embedded into a groove formed in the front surface of the silicon substrate; vertical conductive through holes are formed in a region outside the groove formed in the front surface of the silicon substrate; the functional chip can be used for conducting electricity to the back surface of the silicon substrate; and a rearrangement wire and a welding ball are arranged on the front surface and back surface of the silicon substrate. The structure has the advantages that the thermal expansion coefficients of the silicon substrate and the chip are close so that the packaging structure has good reliability; the structure can realize 3D packaging interconnection; the silicon substrate is adopted, a thin-line and high-density rearrangement wire can be produced, and the requirements on high-density interconnection can be met; and the packaging structure can relatively easily realize miniaturization and thinness, a preparation method is developed and a process is feasible.

Description

technical field [0001] The invention relates to the technical field of electronic packaging, in particular to a fan-out 3D packaging structure embedded in a silicon substrate. Background technique [0002] In the current semiconductor industry, electronic packaging has become an important direction of industry development. The development of packaging technology for decades has made high-density, small-size packaging requirements become the mainstream direction of packaging. [0003] Wafer-level fan-out packaging, by reconstructing the wafer and wafer-level rewiring method, the I / O is covered with the rewiring area array on the package surface, so as to expand the I / O pitch and meet the next level of interconnection pitch requirements. At present, the materials for reconstituting wafers are mainly molding compounds, or organic materials such as prepregs for substrate packaging, to realize the plastic packaging of functional chip fan-out structures, and finally cut into sing...

AI Technical Summary

Problems solved by technology

[0011] In order to solve the above technical problems, the present invention proposes a fan-out 3D packaging structure embedded in a silicon substrate, using a silicon substrate instead of molding compound or other non-silicon materials as the fan-out matrix, which solves the problems caused by the reconstruction of the wafer by the molding compound material. A series of problems, such as warpage and thermal expansion coefficient mismatch; use mature technology on silicon substrates to prepare high-density wiring; various methods can be used to fabricate vertical conductive vias on silicon substrates to achieve three-dimensional vertical interconnection

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