An Adaptive Delay Locked Loop

Abstract

The invention discloses a self-adaptive delay phase-locked loop. The self-adaptive delay phase-locked loop comprises a frequency detection circuit, a DLL delay chain, a feedback delay circuit, a phase discriminator, a DLL controller and an output driver; the input end of the DLL delay chain is connected with an input clock, the output end is connected with the input end of the feedback delay circuit; two input ends of the phase discriminator are respectively connected with the input clock and the output end of the feedback delay circuit, the output end of the phase discriminator is connected with the DLL delay chain through the DLL controller; the input end of the frequency detection circuit is connected with the input clock, and the output end is connected with the DLL delay chain. The frequency detection circuit is added in the traditional DLL circuit so as to control the step size of the DLL delay chain according to a frequency detection result of the input clock, two key indexes of precise and maximum support cycle can be self-adaptively and simultaneously considered under different applications.

Description

technical field [0001] The invention relates to the technical field of delay-locked loops, in particular to an adaptive delay-locked loop. Background technique [0002] Delay-locked loop (DLL) circuits are widely used in clock distribution networks for microprocessors, memory interfaces, interfaces between chips, and large-scale integrated circuits, such as those containing double data rate synchronous dynamic random access memory (DDR SDRAM). Semiconductor memory devices. DLL is used for clock synchronization to solve the clock skew problem, so that the clock delay within the chip or between chips has enough margin, thereby improving the timing function of the system. [0003] The DLL circuit has two key indicators: precision and the maximum support period. These two parameters are related to the step length of the DLL delay chain in the circuit structure, and they need to be compromised, which cannot be considered in different applications. [0004] Traditional DLL circu...

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Problems solved by technology

[0008] Disadvantages: It is difficult for DLL circuits to take into account the two key indicators of precision and maximum support cycle at the same time under different applications. If the step length of the DLL delay chain is too small, it cannot support a larger clock cycle at low frequencies. If the DLL delay If the chain step length is too large, high precision cannot be guaranteed at high frequencies

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