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A Method of Random Test Program Generation

A technology of program generation and random testing, applied in the field of electronics, can solve the problems such as the difficulty of guaranteeing the validity of random testing programs and the difficulty of result detection, and achieve the effect of solving the relatively difficult result detection, simplifying constraints, solving problems, and reducing labor costs.

Active Publication Date: 2018-12-18
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The embodiment of the present invention solves the technical problem that the validity of the random test program in the prior art is difficult to guarantee and the result detection is relatively difficult by providing a method for generating a random test program

Method used

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  • A Method of Random Test Program Generation
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  • A Method of Random Test Program Generation

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Experimental program
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Embodiment approach 2

[0077] Embodiment 2: The embodiment of running the segmented process to generate the relevant instruction parameters of the jump instruction includes the following steps:

[0078] Step 1: Calculate the start address of the serve segment corresponding to the text segment where the target jump instruction is located, wherein the serve segment is the address segment where the relevant instruction parameters are located.

[0079] The target jump instruction and related instruction parameters belong to two different sections of code, the two sections of code are respectively ".text" section and ".serve" section, where ".text_i" and ".serve_i" are a set of corresponding segment, ".text_j" and ".serve_j" are another set of corresponding segments. The ".text section" where the target jump instruction is located should jump to ".serve". The size of each ".text" section is fixed at 30,000 words, and the corresponding ".serve" section is followed by the ".text" section. The starting add...

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Abstract

The invention discloses a random test program generating method. The method comprises the following steps: 1, randomly selecting an instruction; 2, running an instruction collision detection procedure, and selecting instruction parameters of the instruction selected in step 1; 3, judging the instruction selected in step 1 is a target jump instruction or not, if yes, generating related instruction parameters of the target jump instruction, then executing step 4, and if no, directly executing step 4; 4, executing a reference model based on an instruction set, judging whether all instruction parameters of the cycle are accepted or not, if yes, executing step 5, and if no, returning to step 1; 5, generating one or more test instructions based on all the instruction parameters of the cycle; 6, judging whether the number of preset instructions is reached or not, if yes, ending the cycle, and if no, returning to step 1. By means of the random test program generating method, the technical problems that in the prior art, effectiveness of a random test program is difficult to guarantee, and result detection is comparatively difficult to conduct are solved.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a method for generating a random test program. Background technique [0002] With the increasing complexity and integration of integrated circuit design, the challenges encountered in functional verification of integrated circuits are also increasing. Functional verification has been recognized as a bottleneck in hardware design. Processor verification methods can be roughly divided into two categories: formal verification and simulation-based verification. The method of formal verification has made great progress in recent years, but it is suitable for the verification of relatively small modules. Therefore, the simulation-based verification method is still the main technique for the functional verification of microprocessors. Instruction-level verification is a method widely used in current microprocessor functional verification. [0003] Manually written test programs ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/36
CPCG06F11/3684G06F11/3688
Inventor 罗汉青梁利平王志君
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI