A terminal structure of a semiconductor device top layer metal and its manufacturing method
A top metal, terminal structure technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve the problems of narrowing the scribing channel of the corrosion process window and increasing the number of chips, so as to reduce the difficulty of the process and improve the reliability. performance, avoid the effect of the packaging process
Active Publication Date: 2018-08-10
HANGZHOU LION MICROELECTRONICS CO LTD
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Problems solved by technology
[0005] In view of the defects of the above-mentioned prior art, the object of the present invention is to provide a semiconductor device, the top layer metal terminal structure of the device structure can make the multi-layer metal corrosion interface morphology easy to control, the corrosion process window is larger, and at the same time it can make the scribe The narrowing of the wafer path increases the number of chips on the same area of the wafer and saves the cost of the device; at the same time, it can also avoid the impact of technical defects on the reliability of the device due to poor coverage of metal steps
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example 1
[0045] This embodiment describes in detail the device structure and manufacturing method in which the terminal structure of the top layer metal of the present invention is applied to a trench Schottky barrier diode of a semiconductor device. Such as Figure 4 It is a structural diagram of a trench Schottky barrier diode device in the prior art; Figure 5 It is the structural diagram of the trench Schottky barrier diode device of the present embodiment, Figure 5 In this device, the terminal structure of the top metal of the present invention is applied, and the change of the terminal 11a structure of the two top metals can be clearly seen from the two figures.
[0046] Such as Figure 6 is to manufacture this example as Figure 5 Process flow diagram of a trench Schottky barrier diode. The specific description is as follows:
[0047] refer to Figure 6 , firstly perform the substrate preparation step (S10). In the substrate preparation step, a substrate is prepared, and...
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The invention discloses a terminal structure of a top layer metal of a semiconductor device, wherein the semiconductor device includes a chip area realizing the function of the semiconductor device, a scribing lane surrounding the chip area, an insulating dielectric layer extending from the chip area to the scribing lane, and a top layer metal; wherein The scribing lane is a groove structure, and the groove is arranged on the front surface of the epitaxial layer, and the sidewall of the groove is located at the junction of the scribing lane and the chip area, which forms the terminal of the top layer metal of the present invention. The invention also discloses a method for manufacturing the terminal of the top layer metal of the semiconductor device of the invention. The terminal structure of the top layer metal formed in the present invention is easy to control the corrosion interface morphology of the top layer metal, and can form a steep corrosion boundary; and the structure design increases the process window of the top layer metal photolithography and corrosion; it can also reduce the scribe wafer lanes to save cost; at the same time, incomplete dies on the edge of effective dies on the wafer can also be screened out during probe testing.
Description
technical field [0001] The invention relates to a semiconductor device, in particular to a terminal structure of a top layer metal of a semiconductor discrete device and a manufacturing method thereof. Background technique [0002] In current semiconductor devices, the terminal structure of the top metal is generally planar, that is, the terminal of the top metal is the surface of a flat insulating dielectric layer. as attached figure 1 Shown is a schematic diagram of the terminal structure of the top layer metal of the semiconductor device in the prior art. The main structure of the semiconductor device can be simply divided into two regions, that is, the chip region 100 for realizing the semiconductor function and the scribing lane 200. Both regions are formed on a substrate typically comprising 31 (eg N + Silicon wafer: N-type heavily doped silicon wafer) and the epitaxial layer 32 formed by epitaxial growth on the substrate 31 (such as N - Epitaxial wafer: N-type ligh...
Claims
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IPC IPC(8): H01L27/02H01L29/78H01L29/06H01L21/311H01L21/82
CPCH01L21/31105H01L21/82H01L27/0207H01L29/0688H01L29/7833H01L29/7839H01L2229/00
Inventor 张瑞丽
Owner HANGZHOU LION MICROELECTRONICS CO LTD