SRAM type FPGA trigger single-event upset resistance performance assessment system and method

Abstract

The present invention provides a SRAM type FPGA flip-flop anti-single event effect performance evaluation system and method. The test system includes a host computer and a test board; the test board includes a control processing FPGA, configuration PROM, refresh chip, storage PROM, SRAM and a Test the FPGA; the host computer is responsible for process control and data processing; the test board is responsible for processing the commands sent by the host computer and performing trigger single event flip detection. The present invention uses the built-in CAPTURE module of the FPGA to capture the trigger data into the configuration memory and read back the comparison to complete the static test of the trigger SEU (Single-Event Upset), and use the shift register chain configured by the trigger to input and output data Sequence comparison is used to complete the flip-flop SEU (Single-Event Upset) dynamic test, and the system can perform a stable and reliable evaluation of the anti-single event effect performance of the SRAM-type FPGA flip-flop.

Description

technical field [0001] The invention relates to a SRAM-type FPGA anti-single-event effect performance evaluation system and method, mainly for single-event upturn effect SEU (Single-EventUpset), belonging to the field of FPGA testing and irradiation testing. Background technique [0002] The application of SRAM type FPGA in the space field requires not only high reliability, but also radiation resistance is a problem that must be considered. When the SRAM type FPGA works normally, the data stored in the flip-flops and memory units often change with the operation of the circuit. These storage units are hit by high-energy particles while the data remains stable and the data changes. Whether there is a difference in the single-event flipping cross-section under the two cases of being hit by high-energy particles during the process is of great significance to the reliability evaluation of the SRAM-type FPGA working in the space radiation environment. Flip-flops are widely distr...

AI Technical Summary

Problems solved by technology

This method is complex and inaccurate. An even number of flips and flip-flops at the same position in the two shift register chains will cause the method to miss a judgment.

[0004] The existing patents mainly include: (1) A single particle radiation test system and method based on JTAG interface, application number: 201410706041.2, publication number: 104483622A, the application does not involve trigger testing

(2) SRAM-type FPGA single event effect test system and method, application number: 201110214108.7, publication number: 102332307A, the patent only involves the static test of the flip-flop, and does not explain the dynamic testing of the flip-flop; the refresh operation involved in this patent Controlled by the single-chip processor, no refresh chip is used

(3) A SRAM-type FPGA single-particle irradiation test system and method, application number: 201310724722.7, publication number: 103744014A, which macroscopically expounds the tests of FPGA configuration memory, block memory, triggers, etc., about the trigger test not elaborated

[0005] In a word, the above-mentioned prior art cannot accurately and comprehensively evaluate the anti-single event effect performance of the FPGA flip-flop. The present invention overcomes the deficiencies of the prior art and provides an accurate and reliable evaluation system and method for the anti-single event effect performance of the FPGA flip-flop

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