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A Novel High Sensitivity Sensitive Amplifier with Symmetrical Output Edge

A sensitive amplifier and high-sensitivity technology, which is applied in the direction of instruments, static memory, digital memory information, etc., to achieve the effect of reducing power consumption, reducing delay speed, and improving sensitivity

Active Publication Date: 2019-01-04
北京大学(天津滨海)新一代信息技术研究院
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] The present invention aims at the defects of the sensitivity of the existing sensitive amplifier, and proposes a novel high-sensitivity sensitive amplifier with symmetrical output along the

Method used

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  • A Novel High Sensitivity Sensitive Amplifier with Symmetrical Output Edge
  • A Novel High Sensitivity Sensitive Amplifier with Symmetrical Output Edge
  • A Novel High Sensitivity Sensitive Amplifier with Symmetrical Output Edge

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Embodiment Construction

[0020] The present invention will be further described below through specific embodiments and accompanying drawings.

[0021] The sense amplifier structure of the present invention is no longer limited to the logic of the SR latch, but introduces a new slave latch controlled by the clock according to the overall function of the sense amplifier, which is sensitive to the first-stage pulse The generator circuit has a more symmetrical load with a structure like Figure 4 shown. The first-stage pulse generator used by the sense amplifier is the same as the traditional structure. Figure 4 The structure of the SR latch shown in the second stage is: the whole structure is composed of two inverters, 6 PMOS (Mp1~Mp6) transistors and 6 NMOS (Mn1~Mn6) transistors, the pull-up path and the pull-down The path is very symmetrical, S' and R' are the input nodes of the SR latch, CLK and CLKB are two complementary clocks, and Q and Q' are differential output nodes.

[0022] Figure 4 The ...

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Abstract

The invention relates to a novel high-sensitivity sensitiveness amplifier with output edges symmetrical.A first-level pulse generator used for the sensitiveness amplifier is the same as a traditional structure, a second-level SR latch is structurally composed of two phase inverters, six PMOS (Mp1-Mp6) transistors and six NMOS (Mn1-Mn6) transistors, and control of two-phase complementary clocks, namely CLK and CLKB, is adopted.The novel high-sensitivity sensitiveness amplifier has the advantages of an improved structure of Nikolic, and the output ascending edge and the output descending edge are quite symmetrical; due to the fact that clock control is introduced to the second level, load tubes of the first level are reduced, so that delay of the output data edges is reduced, the speed is higher, and meanwhile power consumption is reduced; due to the fact that at the judgment moment, symmetry of the first-level difference load is greatly improved, and the novel high-sensitivity sensitiveness amplifier has quite high sensitivity.

Description

technical field [0001] The invention belongs to the technical field of high-speed data communication integrated circuits, and is a new and improved sensitive amplifier structure, which can increase the sensitivity by an order of magnitude without sacrificing power consumption and speed, so it can greatly improve the efficiency of many module structures. Performance, such as allowing CDR (clock data recovery circuit) to better judge the corresponding relationship between data clocks according to the sampling conditions of data edges. The structure can be widely used in various data communication transmitter or transceiver systems. Background technique [0002] figure 1 It is a traditional sense amplifier structure, which is mainly composed of the pulse generator of the first stage and the SR latch of the second stage. In the pulse generator circuit of the first stage, D and D' represent the differential input signal, S' and R' represent the two input nodes of the SR latch, ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C7/06
CPCG11C7/062
Inventor 盖伟新李士豪
Owner 北京大学(天津滨海)新一代信息技术研究院