System-level wafer packaging structure and packaging method

Abstract

The invention provides a system-level wafer packaging structure. The system-level wafer packaging structure comprises a substrate wafer provided with a circuit, an adapter plate arranged on the substrate wafer, multiple function chips which are arranged on the adapter plate and have same heights, and a packaging body used for packaging the multiple function chips, wherein positioning convex points and positioning grooves or positioning grooves and positioning convex points used for fixedly clamping the function chips on the adapter plate are formed on the lower surface of the function chips and the upper surface of the adapter plate. According to the system-level wafer packaging structure, the positioning convex points and the positioning grooves on the adapter plate and the function chips are employed to replace a traditional mounting mode, so mounting alignment precision is substantially improved, the function chips are further prevented from deviating in a bonding process, the production yield is substantially improved, moreover, in a mounting and bonding process, all the function chips can realize merging and eutectic bonding onto the adapter plate at one time, multiple times of mounting and bonding in the traditional mode can be prevented, technology steps are greatly reduced, and production efficiency is substantially improved.

Description

technical field [0001] The invention relates to wafer packaging technology, in particular to a system-level wafer packaging structure and packaging method. Background technique [0002] Integrating multiple chips with different functions in one unit can form a system-on-chip to realize electrical functions. In the existing technology, the packaging process of system-on-chip usually adopts wafer-level packaging, specifically: bonding an adapter board on the substrate wafer, and then mounting multiple functional chips in stages (through flux, etc. Bonded on the adapter board), bonding, and finally packaged as a whole, and then sliced ​​to form an independent system-on-chip after packaging. The problem existing in the prior art is that each functional chip needs to be mounted and bonded on the adapter board once, and finally packaged as a whole, which has a long process, slow speed and low efficiency. Contents of the invention [0003] In order to solve the above problems, ...

AI Technical Summary

Problems solved by technology

The problem in the existing technology is that each functional chip needs to be placed on the adapter board once, bonded, and finally packaged as a whole. The process is long, slow and inefficient.

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