Probability circuit simulation method based on steepest descent method and bisection method

Abstract

The invention discloses a probability circuit simulation method based on a steepest descent method and a bisection method. The probability circuit simulation method comprises following steps: (1) determining a corresponding relation between a probability unit and an output signal and determining a "gradient" relation therebetween at the same time; (2) acquiring a probability unit combination matrix with respect to each individual output signal, and meeting required precision requirements by using the bisection method to adjust error probabilities; and (3) carrying out overall optimization so as to obtain a final result, allowing a value of each probability unit to be a maximum value and a minimum value in each row in step 2 to obtain two groups of probability combinations and carry out simulation, finding out an output signal, whose error probabilities are at two sides of a target value and error probability difference value is the biggest in two groups of tests, using the bisection method to optimize the final result again and repeating the above steps until all the output error probability values reach a required precision. The probability circuit simulation method is advantageous in that a probability unit needing to be adjusted can be chosen in a quite precise manner during adjustment of a probability value; an error probability value of the probability unit is adjusted in a quite precise manner; and more energy is acquired and saved.

Description

technical field [0001] The invention relates to a probability-based circuit simulation technology, relates to rapidly adjusting the probability value of a probability unit, and specifically relates to a probability circuit simulation method based on a steepest descent method and a dichotomy method. Background technique [0002] With the development of the IC industry, while the chip processing speed is rapidly increasing, the energy consumption is also increasing. As the size of complementary metal oxide semiconductor CMOS devices enters the nanometer era, various internal interference factors affect the electrical characteristics of CMOS devices. The impact is also becoming more apparent. At the same time, with the accelerated popularization of various electronic products, people hope to reduce power consumption of devices while expecting higher hardware performance. In response to the above problems, researchers have proposed the concept of PCMOS (Probabilistic complement...

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Problems solved by technology

[0006] The purpose of the present invention is to provide a probabilistic circuit simulation method based on the steepest descent method and the dichotomy method. In this case, the error probability can be adjusted faster and more accurately, and the adjustment and simulation caused by the lack of regularity can be solved to a certain extent. time consuming problem

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