Digital frequency division phase-locked loop

Abstract

The invention provides a digital frequency division phase-locked loop comprising a time-to-digital converter, a digital loop filter, a digital controlled oscillator, a feedback divider, a sigma-delta modulator, and a correction device. The correction device is used to compensate the digital signals output by the time-to-digital converter based on a frequency control character and a frequency division control character generated by the sigma-delta modulator in order to acquire correction signals. The digital loop filter is used for the digital filtering of the correction signals in order to acquire oscillator frequency control signals, which are used as the output signals of the digital controlled oscillator. The correction device is used to compensate the digital signals output by the time-to-digital converter based on the frequency control character and the frequency division control character, and therefore the improvement of the time-to-digital converter is not required, and then the non-linear correction of the digital frequency division phase-locked loop is realized with low costs.

Description

technical field [0001] The present application relates to the field of electronic information, in particular to a digital frequency-division phase-locked loop. Background technique [0002] In radio frequency (Radio Frequency, RF) transceivers, a frequency synthesizer based on a phase-locked loop (Phase-Locked Loop, PLL) structure is widely used to generate a local oscillator (Local Oscillator, LO) signal, which is used to complete the radio frequency The frequency shifting operation of the signal. Due to the advantages of lock time, integrated phase noise, and design flexibility, the digital fractional frequency division PLL that can realize not only integer frequency division but also fractional frequency division is more advanced than the integer frequency division PLL. Wide range of applications. [0003] In the digital fractional phase-locked loop, the time-to-digital converter (Time-to-Digital Converter, TDC) is one of the important analog components, and its linear ...

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Problems solved by technology

[0004] For the current common TDC structure, the reasons affecting its linearity mainly include several aspects such as device mismatch and layout design mismatch. In order to improve the linearity of TDC, it is usually necessary to compare power consumption, area and complexity. Big cost, so hard to implement

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