Anti-single-event transient reinforcement SOI member and manufacture method for the same

Abstract

The invention relates to the microelectronic technology field. The invention discloses an anti-single-event transient reinforcement SOI member, comprising a substrate, a buried oxide layer, a semiconductor body region, a drain region, a source region, a grid region, gridside walls, LDD regions and a heavily doped source extending region; the buried oxide layer is arranged above the substrate; the semiconductor body region, the source region and the drain region are arranged above the buried oxide layer; the semiconductor body region is positioned between the source region and the drain region; the LDD regions are positioned on two side ends of the semiconductor body region and in contact with the source region and the drain region; the grid region is positioned above the semiconductor body region; the two side gridside walls are arranged on two sides of the grid region and above the LDD regions; the source extending region is arranged among the source region, the semiconductor body region and the buried oxide layer; and the doping types of the source extending region and the source region are opposite. The invention also discloses a manufacture method for the anti-single-event transient reinforcement SOI member. The anti-single-event transient reinforcement SOI member and the manufacture method for the same can effectively inhibit SOI member single-event overturning and the single-event transient effect which are caused by single-event radiation, and the technology is simple and compatible with the current technology.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and in particular relates to an anti-single particle transient reinforced SOI device and a preparation method thereof. Background technique [0002] SOI (Silicon-on-Insulator) technology refers to the material preparation technology of forming a single crystal semiconductor silicon thin film layer with a certain thickness on the insulating layer and the process technology of manufacturing semiconductor devices on the thin film layer. SOI technology can realize full dielectric isolation of devices. Compared with bulk silicon technology isolated by PN junction, it has the advantages of no latch, high speed, low power consumption, high integration, high temperature resistance, and strong radiation resistance. It is widely used in high-speed, low power consumption, and radiation-resistant circuits. [0003] According to the thickness of SOI silicon film and the doping concentration and oper...

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Problems solved by technology

This method also requires the introduction of additional Ge elements, and the junction depth of the SiGe junction is difficult to control

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