Half-rate clock-data recovery circuit and method thereof

Abstract

The invention discloses a half-rate clock-data recovery circuit and a method thereof. A half-rate clock data recovery circuit comprises a detector receiving data alternating between even and odd symbols and further receives a four-phase clock. The detector outputs a phase error signal to a phase dissect circuit which outputs an even-symbol phase error and an odd-symbol phase error, which are input to filters to produce first and third control signals. A first 2-bit ADC also receives the even and odd data and outputs even symbol data in accordance with a second phase of the four-phase clock. A second 2-bit ADC also receives the data and outputs odd symbol data in accordance with a fourth phase of the four-phase clock. The even and odd symbol data are input into respective vertical eye monitors which output second and fourth control signals. A quadrature clock generator adjusts the clock based on the control signals. A method uses the half-rate clock data recovery circuit.

Description

technical field [0001] The invention relates to a clock-data recovery circuit (clock-data recovery circuit). Background technique [0002] Those skilled in the art should understand various terms and basic concepts related to microelectronics used in the description, such as: signal, clock, half-rate (half-rate), edge (of clock), binary, vertical eye opening ( vertical eye opening), binary phase detector, filter, voltage-controlled oscillator, ternary, current mode, charge pump, and analog-to-digital converter (ADC), etc. These terms and basic concepts are obvious to those skilled in the art, so they will not be explained in detail here. [0003] The known half-rate clock data recovery circuit has a symbol period T s A circuit of serial binary symbols for a stream of signals. This circuit generates a four-phase recovered clock aligned to the timing of the received signal. Among them, the period of the four-phase recovered clock is 2T s , that is, the symbol period T s ...

AI Technical Summary

Problems solved by technology

Here, the known half rate clock data recovery circuit 100 does not work properly because there is no guarantee that each phase of the four phase recovered clock is optimally timed (relative to the received signal)

Images