High-K metal gate device and preparation method therefor
A metal gate and device technology, which is applied in the field of high-k metal gate devices and their preparation, can solve the problems of unsatisfactory stability of high-k metal gate PMOS devices, inability to effectively block the diffusion behavior of upper and lower metal elements, and eliminate residual Thickness fluctuation, the effect of improving stability
Active Publication Date: 2016-10-12
SHANGHAI HUALI MICROELECTRONICS CORP
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Problems solved by technology
At the same time, as the work function intermediate layer of PMOS, the lattice structure of TaN also determines that it cannot effectively block the diffusion behavior of metal elements in the upper and lower layers under certain thermodynamic conditions.
Therefore, for some processes, the stability of high-k metal gate PMOS devices is not ideal
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[0025] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.
[0026] The following is attached Figure 1-8 The present invention will be described in further detail with specific examples. It should be noted that the drawings are all in a very simplified form, using imprecise scales, and are only used to facilitate and clearly achieve the purpose of assisting in describing the present embodiment.
[0027] see figure 1 , the high-K metal gate device of this embodiment includes an NMOS region and a PMOS region, the silicon substrate 01 in the NMOS region and the PMOS region has a trench, an oxide layer 02 is formed at the bot...
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Abstract
The invention provides a high-K metal gate device and a preparation method therefor. A silicon material layer is used as the barrier layer of the lower layer silicon nitride of an NMOS region; the silicon is fully dispersed to the upper layer silicon nitride and the lower layer silicon nitride through an annealing process to form a TiSiN intermediate layer of a PMOS region and a TiSiN layer of the NMOS region; the TiSiN material can block the subsequent downward diffusion of the upper layer metal atoms, so that the stability of the metal gate device is improved; in addition, the residual silicon material layer on the NMOS region can be removed subsequently, so that the residual thickness fluctuation of the silicon material layer and the caused fluctuation of the NMOS threshold voltage can be eliminated; therefore, the stability of the NMOS device is further improved; and the stability of the high-K metal gate device is improved as a whole.
Description
technical field [0001] The invention relates to the technical field of semiconductor technology, in particular to a high-K metal gate device and a preparation method thereof. Background technique [0002] With the rapid development of VLSI technology, the size of MOSFET devices is continuously reduced, which usually includes the reduction of the channel length of MOSFET devices, the thinning of gate oxide layer thickness, etc. to obtain faster device speed. However, when it develops to the ultra-deep submicron level, especially when the technology node is 45nm and below, it can no longer bear the high leakage caused by the continuous reduction of the gate oxide thickness. The industry has introduced high-k and metal gate designs at 45nm and below. [0003] In the high-k metal-gate semiconductor process, tantalum nitride (TaN) is usually selected as the barrier layer for the removal of the P-type work function layer TiN in the NMOS region, and the TiN etching process itself ...
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IPC IPC(8): H01L29/78H01L21/28H01L21/283H01L29/51
CPCH01L21/28229H01L21/283H01L29/517H01L29/78H01L21/823842H01L21/28088H01L29/4966H01L27/092H01L29/4236H01L21/324H01L21/823828H01L21/823857H01L29/518
Inventor 何志斌景旭斌
Owner SHANGHAI HUALI MICROELECTRONICS CORP