Memory device

Abstract

The invention discloses a memory element, which includes a multi-layer stacked structure with a plurality of conductive layers. A plurality of columnar bodies perpendicular to the base material, each columnar body comprising a plurality of memory cells connected in series, are located at intersections of the columnar body and the conductive layers. A number of serial select lines are located above these conductive layers. Multiple bit lines are located above the serial select lines, and the columns are arranged on a regular grid with non-rectangular parallelogram unit cells. These columns are arranged to form a plurality of parallel columnar flat cables, and each columnar flat cable crosses these bit lines at an acute angle of θ>0°; each columnar flat cable has n (n>1) columns, All columns cross a particular common string select line of these string select lines. This arrangement allows greater bit line density and higher data processing rate due to increased parallel operations, and reduces the number of serial selection lines, reducing interference, power consumption, and unit cell capacitance.

Description

technical field [0001] The present invention relates to a kind of high density memory device (high density memory devices), especially relates to a kind of containing multi-layer storage unit planar layer (multiple planes of memorycells) and arranges to form three-dimensional (Three-Dimension, 3D) ) memory element of the array, that is, a parallelogram memory cell design of a high-speed vertical channel three-dimensional NAND memory. [0002] This application is a Continuation-In-Part of U.S. Application No. 14 / 157,550, filed January 17, 2014, entitled THREE-DIMENSIONAL SEMICONDUCTOR DEVICE, hereby incorporated by reference The full text of this patent is included in this specification by way of incorporated by reference. [0003] The content of this application can also be incorporated by reference, citing (makes reference) an application filed on the same day as this case, No. 14582963, entitled TWISTED ARRAY DESIGN FOR HIGH SPEEDVERTICAL CHANNEL 3D NAND MEMORY), the inven...

AI Technical Summary

Problems solved by technology

Since the increase of the storage layer also increases the number of serial selection lines 12, it also leads to an increase in power consumption and slows down the operation speed of the element.

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