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Signed probability calculating unit based on probability Turbo decoder

A probability calculation and decoder technology, applied in the field of decoding algorithms, can solve the problems of low precision, high complexity and slow convergence of computing units, and achieve the effect of overcoming the low precision of computing units

Active Publication Date: 2016-10-26
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The purpose of the present invention is to overcome the problems of low accuracy, slow convergence and high complexity of the calculation unit in the existing probability turbo decoder, and provide a novel calculation unit implementation method for the probability turbo decoder based on Log-MAP , which includes a signed probability adder and a probability normalization unit

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  • Signed probability calculating unit based on probability Turbo decoder
  • Signed probability calculating unit based on probability Turbo decoder
  • Signed probability calculating unit based on probability Turbo decoder

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Embodiment 1

[0055] For the probability turbo decoder based on Log-MAP, the present invention provides a probability calculation unit based on the probability turbo decoder, the probability adder in the probability calculation unit includes a random bit calculation module 301, a sign bit calculation module 302 And a saturation carry storage update module 303;

[0056] The random bit calculation module 301, the sign bit calculation module 302 and the saturation carry storage update module 303 are connected any two;

[0057] The random bit calculation module 301 completes the random bit calculation;

[0058] The sign bit calculation module 302 completes the sign bit calculation;

[0059] The saturated carry storage update module 303 realizes the storage update of the saturated carry.

[0060] Further, the random bit calculation module 301 includes an exclusive OR gate 3001, an exclusive OR gate 3002, a first OR gate 3003 and a first multiplexer 3006;

[0061] The XOR gate 3001 inputs the ...

Embodiment 2

[0085] The probability calculation unit described in embodiment 2 also includes a probability normalization unit, Figure 5 The implementation structure of the 8-input probability normalization unit in the forward state metric calculation module 202 and the backward state metric calculation module 203 is given. Further, the probability normalization unit in the probability calculation unit includes an input module 401, a second full adder 402, a second register 403, a fourth OR gate 404, a fifth OR gate 405, an input judgment module 410 and a TFM module 420;

[0086] The input module 401, the second full adder 402, the second register 403 and the fourth OR gate 404 are sequentially connected;

[0087] The second register 403 stores a saturated carry result, and the fourth OR gate 404 realizes a function of judging whether the saturated carry result is greater than 0;

[0088] The input judging module 410 is connected to the input module 401, which includes a sixth gate 406 w...

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Abstract

The invention discloses a signed probability calculating unit based on a probability Turbo decoder. The signed probability calculating unit is characterized in that a probability adder in the probability calculating unit comprises a random bit calculating module, a sign bit calculating module and a saturated carry storage updating module. The random bit calculating module completes random bit calculation. The sign bit calculating module completes sign bit calculation. The saturated carry storage updating module realizes storage and updating of saturated carry. Compared with the conventional probability adder and probability normalization method, the probability calculating unit discloses by the invention has the advantages that the precision is higher, the convergence is rapid, and the decoding performance of the decoder is substantially improved when the probability calculating unit is applied to the probability Turbo decoder. The probability Turbo decoder realized based on the method provided by the invention is high in capacity, low in complexity and high in performance.

Description

technical field [0001] The invention relates to the technical field of wireless communication, in particular to a decoding algorithm in a communication system including Turbo code as a channel code, which can be applied to the third generation, fourth generation and even fifth generation mobile communication systems. Background technique [0002] Turbo code is a forward error correction code approaching the Shannon limit, which can effectively improve the reliability of communication systems, and has been adopted by communication protocols such as 3GPP and LTE / LTE-Advanced. However, the complexity of the optimal decoding algorithm is too high to be applied to the actual system. Therefore, the academic community immediately proposed a low-complexity MAP decoding algorithm and its logarithmic domain Log-MAP decoding algorithm and approximate algorithm Max- Log-MAP decoding algorithm. However, the above-mentioned algorithms are all sequential decoding algorithms, resulting in ...

Claims

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Application Information

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IPC IPC(8): H03M13/29
CPCH03M13/2957
Inventor 张珍兵胡剑浩陈杰男
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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