Multichannel audio signal parallel collection device

Abstract

The invention discloses a multichannel audio signal parallel collection device. The collection device comprises an FPGA processing unit, multiple audio decoding chips and a processor; the multiple audio decoding chips are electrically connected to the FPGA processing unit; the FPGA processing unit is electrically connected with the audio decoding chips and the processor and used for receiving audio data of all the audio decoding chips, namely audio data of multiple channels, fusing and recoding the audio data, increasing the transmission rate with the processor and transmitting the recoded data to the processor. Compared with a traditional integrated A / D chip scheme, cost and power consumption of a whole system are greatly lowered through the collection device.

Description

technical field [0001] The invention relates to the field of speech recognition, and further relates to a multi-channel signal parallel acquisition device. Background technique [0002] With the development of speech recognition and dialogue systems, intelligent speech interaction technology has attracted more and more attention. Voice interaction is inseparable from the acquisition of audio signals. Parallel acquisition of multi-channel signals has always been the core technology of signal processing, especially in the field of array-based signal processing. [0003] Array signal processing often needs to collect multiple sensors at the same time in order to use the phase difference information between various signals to design corresponding array signal processing algorithms. In the design process of this type of acquisition system, there are often many data channels, large data throughput, fast data transmission rate, and high real-time requirements. [0004] At present...

AI Technical Summary

Problems solved by technology

However, although the commonly used processors on the market generally have I2S interfaces, they do not support TDM mode. This means that for multi-channel Codecs, the processor needs to have multiple 12S interfaces for docking, which undoubtedly increases the difficulty of processor selection. and cost; and this mode increases the difficulty of data synchronization between channels

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