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Circuit for loading FPGA configuration file through serial port

A configuration file and circuit technology, applied in electrical digital data processing, instruments, etc., can solve the problems of inability to easily expand the programming method and high cost, and achieve the effect of high price, small capacity, and reduced hardware cost.

Pending Publication Date: 2016-11-16
NANJING APAITEK TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Currently, the commonly used method of loading FPGA configuration files is to configure the FPGA through the AS interface or JTAG interface of the FPGA, such as figure 1 As shown, it uses the USB Blaster programmer to burn the configuration file from the computer to the external FLASH, and the FPGA loads the configuration file from the external FLASH to the internal RAM of the FPGA. In the process, a dedicated configuration chip for the FPGA is required, and the cost is relatively high.
[0003] Moreover, the current environment where the product is located is relatively strict, and the method of updating the FPGA program is becoming more and more important to the product. Since the commonly used programming method requires a USB Blaster programmer, it is decided that the programming method cannot be easily expanded, and a program is required. A circuit with more scalable FPGA configuration files, and its programming method is flexible

Method used

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  • Circuit for loading FPGA configuration file through serial port
  • Circuit for loading FPGA configuration file through serial port

Examples

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Embodiment Construction

[0015] Such as figure 2 As shown, the invention discloses a circuit for loading an FPGA configuration file through a serial port, including a single-chip circuit I and an FPGA circuit II. The circuit includes 1 single-chip microcomputer chip, 1 FPGA chip, 1 FLASH chip, and 18 chip resistors. The microcontroller chip U1 is STM32F103RCT6, the flash chip U3 is W25X16, U4 is a two-position DIP switch, U5 is a four-position DIP switch, resistors R7 and R8 are 510Ω, and resistors R1, R9 and R10 are 10KΩ.

[0016] The MCU circuit includes a two-position DIP switch, a W25X16 chip and a STM32F103RCT6 chip, and five resistors R1, R7, R8, R9, R10; pin 60 of the chip U1 is connected to pin 1 of the DIP switch U4, and the chip U1 The 28th pin of the DIP switch U4 is connected to the 2nd pin of the DIP switch; one end of the resistor R7 is connected to 3.3V, and the other end of the resistor R7 is connected to the 2nd corner of the DIP switch U4; one end of the resistor R8 is connected to...

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PUM

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Abstract

The invention relates to a circuit for loading an FPGA configuration file through a serial port inside an active filter product. The circuit comprises a singlechip circuit and an FPGA circuit, wherein the singlechip circuit is electrically connected with the FPGA circuit; the singlechip circuit comprises five resistors including R1, R7, R8, R9 and R10 respectively, a two-digit DIP switch U4, a W25X16 chip U3 and an STM32F103RCT6 chip U1; the FPGA circuit comprises partial pins of an FPGA chip U2, a four-digit DIP switch U5 and 13 resistors including R2, R3, R4, R5, R6, R11, R12, R13, R14, R15, R16, R17 and R18 respectively. The circuit is flexible in programming method and convenient for later maintenance and upgrading of a product.

Description

technical field [0001] The invention relates to a circuit for loading FPGA configuration files into a serial port inside an active filtering product. Background technique [0002] The circuit that loads the FPGA configuration file is an essential part of the active filter product, and it is related to whether the active filter product can operate normally. Currently, the commonly used method of loading FPGA configuration files is to configure the FPGA through the AS interface or JTAG interface of the FPGA, such as figure 1 As shown, it uses the USB Blaster programmer to burn the configuration file from the computer to the external FLASH, and the FPGA loads the configuration file from the external FLASH to the internal RAM of the FPGA. In the process, a dedicated configuration chip for the FPGA is required, and the cost is relatively high. . [0003] Moreover, the current environment where the product is located is relatively strict, and the method of updating the FPGA prog...

Claims

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Application Information

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IPC IPC(8): G06F13/40
CPCG06F13/4022
Inventor 马俊刘明张明仇志凌葛文海
Owner NANJING APAITEK TECH
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